mbed-classic: added nrf51.h from most recent SDK
Upstream mbed doesn't have the correct version of nrf51.h for builds with mbed-classic on mbed.org. This means that builds fail online due to incompatible nrf51.h's. This commit adds the correct version of nrf51.h to our repo.
This commit is contained in:
James Devine
parent
1a8031daf8
commit
0918819fd0
1 changed files with 78 additions and 127 deletions
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@ -1,56 +1,34 @@
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/****************************************************************************************************//**
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* @file nRF51.h
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/*
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* Copyright (c) Nordic Semiconductor ASA
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* All rights reserved.
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*
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* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
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* nRF51 from Nordic Semiconductor.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* @version V522
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* @date 31. October 2014
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* @note Generated with SVDConv V2.81d
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* from CMSIS SVD File 'nRF51.xml' Version 522,
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* 2. Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* @par Copyright (c) 2013, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* * Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
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* contributors to this software may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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*******************************************************************************************************/
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/** @addtogroup Nordic Semiconductor
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* @{
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*/
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/** @addtogroup nRF51
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* @{
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*/
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRF51_H
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#define NRF51_H
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@ -71,7 +49,7 @@ typedef enum {
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DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
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PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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SysTick_IRQn = -1, /*!< 15 System Tick Timer */
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/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
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/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
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POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
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RADIO_IRQn = 1, /*!< 1 RADIO */
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UART0_IRQn = 2, /*!< 2 UART0 */
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@ -117,7 +95,8 @@ typedef enum {
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/** @} */ /* End of group Configuration_of_CMSIS */
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#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
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#include "system_nrf51.h" /*!< nRF51 System */
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#include "system_nrf51.h" /*!< nrf51 System */
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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@ -183,15 +162,6 @@ typedef struct {
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__IO uint32_t TEP; /*!< Channel task end-point. */
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} PPI_CH_Type;
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typedef struct {
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__I uint32_t PART; /*!< Part code */
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__I uint32_t VARIANT; /*!< Part variant */
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__I uint32_t PACKAGE; /*!< Package option */
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__I uint32_t RAM; /*!< RAM variant */
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__I uint32_t FLASH; /*!< Flash variant */
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__I uint32_t RESERVED[3]; /*!< Reserved */
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} FICR_INFO_Type;
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/* ================================================================================ */
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/* ================ POWER ================ */
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@ -300,27 +270,6 @@ typedef struct { /*!< MPU Structure
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} NRF_MPU_Type;
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/* ================================================================================ */
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/* ================ PU ================ */
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/* ================================================================================ */
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/**
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* @brief Patch unit. (PU)
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*/
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typedef struct { /*!< PU Structure */
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__I uint32_t RESERVED0[448];
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__IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
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__I uint32_t RESERVED1[24];
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__IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
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__I uint32_t RESERVED2[24];
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__IO uint32_t PATCHEN; /*!< Patch enable register. */
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__IO uint32_t PATCHENSET; /*!< Patch enable register. */
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__IO uint32_t PATCHENCLR; /*!< Patch disable register. */
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} NRF_PU_Type;
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/* ================================================================================ */
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/* ================ AMLI ================ */
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/* ================================================================================ */
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@ -366,7 +315,7 @@ typedef struct { /*!< RADIO Structure
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__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
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sample is ready for readout at the RSSISAMPLE register. */
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__I uint32_t RESERVED1[2];
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__IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
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__IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
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__I uint32_t RESERVED2[53];
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__IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
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__I uint32_t RESERVED3[64];
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@ -374,11 +323,11 @@ typedef struct { /*!< RADIO Structure
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__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
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__I uint32_t RESERVED4[61];
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__I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
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__I uint32_t CD; /*!< Carrier detect. */
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__I uint32_t RESERVED5;
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__I uint32_t RXMATCH; /*!< Received address. */
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__I uint32_t RXCRC; /*!< Received CRC. */
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__I uint32_t DAI; /*!< Device address match index. */
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__I uint32_t RESERVED5[60];
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__I uint32_t RESERVED6[60];
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__IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
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__IO uint32_t FREQUENCY; /*!< Frequency. */
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__IO uint32_t TXPOWER; /*!< Output power. */
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@ -397,22 +346,22 @@ typedef struct { /*!< RADIO Structure
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__IO uint32_t TEST; /*!< Test features enable register. */
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__IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
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__I uint32_t RSSISAMPLE; /*!< RSSI sample. */
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__I uint32_t RESERVED6;
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__I uint32_t RESERVED7;
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__I uint32_t STATE; /*!< Current radio state. */
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__IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
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__I uint32_t RESERVED7[2];
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__I uint32_t RESERVED8[2];
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__IO uint32_t BCC; /*!< Bit counter compare. */
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__I uint32_t RESERVED8[39];
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__I uint32_t RESERVED9[39];
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__IO uint32_t DAB[8]; /*!< Device address base segment. */
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__IO uint32_t DAP[8]; /*!< Device address prefix. */
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__IO uint32_t DACNF; /*!< Device address match configuration. */
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__I uint32_t RESERVED9[56];
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__I uint32_t RESERVED10[56];
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__IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
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__IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
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__IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
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__IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
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__IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
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__I uint32_t RESERVED10[561];
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__I uint32_t RESERVED11[561];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_RADIO_Type;
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@ -571,39 +520,41 @@ typedef struct { /*!< SPIS Structure
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__O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
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__I uint32_t RESERVED1[54];
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__IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
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__I uint32_t RESERVED2[8];
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__I uint32_t RESERVED2[2];
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__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
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__I uint32_t RESERVED3[5];
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__IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
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__I uint32_t RESERVED3[53];
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__I uint32_t RESERVED4[53];
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__IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
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__I uint32_t RESERVED4[64];
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__I uint32_t RESERVED5[64];
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__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
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__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
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__I uint32_t RESERVED5[61];
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__I uint32_t RESERVED6[61];
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__I uint32_t SEMSTAT; /*!< Semaphore status. */
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__I uint32_t RESERVED6[15];
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__I uint32_t RESERVED7[15];
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__IO uint32_t STATUS; /*!< Status from last transaction. */
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__I uint32_t RESERVED7[47];
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__I uint32_t RESERVED8[47];
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__IO uint32_t ENABLE; /*!< Enable SPIS. */
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__I uint32_t RESERVED8;
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__I uint32_t RESERVED9;
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__IO uint32_t PSELSCK; /*!< Pin select for SCK. */
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__IO uint32_t PSELMISO; /*!< Pin select for MISO. */
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__IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
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__IO uint32_t PSELCSN; /*!< Pin select for CSN. */
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__I uint32_t RESERVED9[7];
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__I uint32_t RESERVED10[7];
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__IO uint32_t RXDPTR; /*!< RX data pointer. */
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__IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
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__I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
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__I uint32_t RESERVED10;
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__I uint32_t RESERVED11;
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__IO uint32_t TXDPTR; /*!< TX data pointer. */
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__IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
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__I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
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__I uint32_t RESERVED11;
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__I uint32_t RESERVED12;
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__I uint32_t RESERVED13;
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__IO uint32_t DEF; /*!< Default character. */
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__I uint32_t RESERVED13[24];
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__I uint32_t RESERVED14[24];
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__IO uint32_t ORC; /*!< Over-read character. */
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__I uint32_t RESERVED14[654];
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__I uint32_t RESERVED15[654];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_SPIS_Type;
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@ -628,35 +579,28 @@ typedef struct { /*!< SPIM Structure
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__IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
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__I uint32_t RESERVED3[2];
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__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
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__I uint32_t RESERVED4;
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__IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
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__I uint32_t RESERVED5;
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__I uint32_t RESERVED4[3];
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__IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
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__I uint32_t RESERVED6[10];
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__I uint32_t RESERVED5[10];
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__IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
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__I uint32_t RESERVED7[44];
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__IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
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__I uint32_t RESERVED8[64];
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__I uint32_t RESERVED6[109];
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__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
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__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
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__I uint32_t RESERVED9[125];
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__I uint32_t RESERVED7[125];
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__IO uint32_t ENABLE; /*!< Enable SPIM. */
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__I uint32_t RESERVED10;
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__I uint32_t RESERVED8;
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SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
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__I uint32_t RESERVED11;
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__I uint32_t RXDDATA; /*!< RXD register. */
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__IO uint32_t TXDDATA; /*!< TXD register. */
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__I uint32_t RESERVED12;
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__I uint32_t RESERVED9[4];
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__IO uint32_t FREQUENCY; /*!< SPI frequency. */
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__I uint32_t RESERVED13[3];
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__I uint32_t RESERVED10[3];
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SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
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__I uint32_t RESERVED14;
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__I uint32_t RESERVED11;
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SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
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__I uint32_t RESERVED15;
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__I uint32_t RESERVED12;
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__I uint32_t RESERVED16[26];
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__I uint32_t RESERVED13[26];
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__IO uint32_t ORC; /*!< Over-read character. */
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__I uint32_t RESERVED17[654];
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__I uint32_t RESERVED14[654];
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__IO uint32_t POWER; /*!< Peripheral power control. */
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} NRF_SPIM_Type;
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@ -1087,9 +1031,13 @@ typedef struct { /*!< NVMC Structure
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__I uint32_t READY; /*!< Ready flag. */
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__I uint32_t RESERVED1[64];
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__IO uint32_t CONFIG; /*!< Configuration register. */
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__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
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union {
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__IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
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__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
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};
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__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
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__IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
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__IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
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__IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
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} NRF_NVMC_Type;
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@ -1134,7 +1082,7 @@ typedef struct { /*!< FICR Structure
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__I uint32_t PPFC; /*!< Pre-programmed factory code present. */
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__I uint32_t RESERVED2;
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__I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
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union {
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__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
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kept for backward compatinility purposes. Use SIZERAMBLOCKS
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@ -1155,7 +1103,6 @@ typedef struct { /*!< FICR Structure
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__I uint32_t RESERVED5[10];
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__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
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mode. */
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FICR_INFO_Type INFO; /*!< Device info */
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} NRF_FICR_Type;
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@ -1174,7 +1121,13 @@ typedef struct { /*!< UICR Structure
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__IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
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__I uint32_t RESERVED0;
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__I uint32_t FWID; /*!< Firmware ID. */
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__IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
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union {
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__IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
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__IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
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};
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__IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
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__IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
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} NRF_UICR_Type;
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@ -1226,7 +1179,6 @@ typedef struct { /*!< GPIO Structure
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#define NRF_POWER_BASE 0x40000000UL
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#define NRF_CLOCK_BASE 0x40000000UL
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#define NRF_MPU_BASE 0x40000000UL
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#define NRF_PU_BASE 0x40000000UL
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#define NRF_AMLI_BASE 0x40000000UL
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#define NRF_RADIO_BASE 0x40001000UL
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#define NRF_UART0_BASE 0x40002000UL
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@ -1266,7 +1218,6 @@ typedef struct { /*!< GPIO Structure
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#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
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#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
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#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
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#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
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#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
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#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
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#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
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@ -1300,7 +1251,7 @@ typedef struct { /*!< GPIO Structure
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/** @} */ /* End of group Device_Peripheral_Registers */
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/** @} */ /* End of group nRF51 */
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/** @} */ /* End of group nrf51 */
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/** @} */ /* End of group Nordic Semiconductor */
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#ifdef __cplusplus
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@ -1308,5 +1259,5 @@ typedef struct { /*!< GPIO Structure
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#endif
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||||
|
||||
|
||||
#endif /* nRF51_H */
|
||||
#endif /* nrf51_H */
|
||||
|
||||
|
|
|
|||
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Reference in a new issue