From 93df986f5854c4ecd793a88a351df5a00456e245 Mon Sep 17 00:00:00 2001 From: James Devine Date: Tue, 2 Feb 2016 15:26:15 +0000 Subject: [PATCH] initial commit before we edit this git repo We are about to update the us_ticker.c implementation so that we can gain increased granularity for the all timer related classes. --- CMakeLists.txt | 117 + api/AnalogIn.h | 103 + api/AnalogOut.h | 121 + api/BusIn.h | 98 + api/BusInOut.h | 117 + api/BusOut.h | 101 + api/CAN.h | 243 + api/CThunk.h | 202 + api/CallChain.h | 181 + api/CircularBuffer.h | 98 + api/DigitalIn.h | 107 + api/DigitalInOut.h | 124 + api/DigitalOut.h | 116 + api/DirHandle.h | 104 + api/Ethernet.h | 170 + api/FileBase.h | 80 + api/FileHandle.h | 119 + api/FileLike.h | 44 + api/FilePath.h | 46 + api/FileSystemLike.h | 104 + api/FunctionPointer.h | 202 + api/I2C.h | 176 + api/I2CSlave.h | 154 + api/InterruptIn.h | 135 + api/InterruptManager.h | 143 + api/LocalFileSystem.h | 103 + api/LowPowerTicker.h | 44 + api/LowPowerTimeout.h | 42 + api/LowPowerTimer.h | 42 + api/PortIn.h | 93 + api/PortInOut.h | 104 + api/PortOut.h | 104 + api/PwmOut.h | 158 + api/RawSerial.h | 90 + api/SPI.h | 245 + api/SPISlave.h | 122 + api/Serial.h | 74 + api/SerialBase.h | 223 + api/Stream.h | 65 + api/Ticker.h | 127 + api/Timeout.h | 59 + api/Timer.h | 91 + api/TimerEvent.h | 56 + api/Transaction.h | 73 + api/can_helper.h | 53 + api/mbed.h | 69 + api/mbed_assert.h | 49 + api/mbed_debug.h | 66 + api/mbed_error.h | 66 + api/mbed_interface.h | 114 + api/platform.h | 30 + api/rtc_time.h | 85 + api/semihost_api.h | 93 + api/toolchain.h | 35 + api/wait_api.h | 66 + common/BusIn.cpp | 82 + common/BusInOut.cpp | 115 + common/BusOut.cpp | 91 + common/CAN.cpp | 86 + common/CallChain.cpp | 90 + common/Ethernet.cpp | 73 + common/FileBase.cpp | 82 + common/FileLike.cpp | 28 + common/FilePath.cpp | 76 + common/FileSystemLike.cpp | 77 + common/I2C.cpp | 128 + common/I2CSlave.cpp | 63 + common/InterruptIn.cpp | 85 + common/InterruptManager.cpp | 93 + common/LocalFileSystem.cpp | 223 + common/RawSerial.cpp | 67 + common/SPI.cpp | 180 + common/SPISlave.cpp | 58 + common/Serial.cpp | 36 + common/SerialBase.cpp | 212 + common/Stream.cpp | 111 + common/Ticker.cpp | 40 + common/Timeout.cpp | 24 + common/Timer.cpp | 73 + common/TimerEvent.cpp | 51 + common/assert.c | 22 + common/board.c | 59 + common/error.c | 33 + common/gpio.c | 61 + common/lp_ticker_api.c | 45 + common/mbed_interface.c | 113 + common/pinmap_common.c | 89 + common/retarget.cpp | 569 + common/rtc_time.c | 89 + common/semihost_api.c | 162 + common/ticker_api.c | 135 + common/us_ticker_api.c | 41 + common/wait_api.c | 30 + hal/analogin_api.h | 39 + hal/analogout_api.h | 42 + hal/buffer.h | 30 + hal/can_api.h | 80 + hal/dma_api.h | 45 + hal/ethernet_api.h | 63 + hal/gpio_api.h | 57 + hal/gpio_irq_api.h | 49 + hal/i2c_api.h | 223 + hal/lp_ticker_api.h | 82 + hal/pinmap.h | 45 + hal/port_api.h | 42 + hal/pwmout_api.h | 49 + hal/rtc_api.h | 42 + hal/serial_api.h | 302 + hal/sleep_api.h | 64 + hal/spi_api.h | 213 + hal/ticker_api.h | 108 + hal/us_ticker_api.h | 78 + module.json | 28 + .../TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h | 725 + .../TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h | 595 + .../TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct | 47 + .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 271 + .../TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h | 42 + .../TARGET_MPS2_M0/cmsis_nvic.c | 54 + .../TARGET_MPS2_M0/cmsis_nvic.h | 54 + .../TARGET_MPS2_M0/peripherallink.h | 53 + .../TARGET_MPS2_M0/system_CMSDK_CM0.c | 92 + .../TARGET_MPS2_M0/system_CMSDK_CM0.h | 80 + .../TARGET_MPS2_M0P/CMSDK_CM0plus.h | 726 + .../TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h | 595 + .../TOOLCHAIN_ARM_STD/MPS2.sct | 47 + .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 271 + .../TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h | 42 + .../TARGET_MPS2_M0P/cmsis_nvic.c | 54 + .../TARGET_MPS2_M0P/cmsis_nvic.h | 54 + .../TARGET_MPS2_M0P/peripherallink.h | 53 + .../TARGET_MPS2_M0P/system_CMSDK_CM0plus.c | 93 + .../TARGET_MPS2_M0P/system_CMSDK_CM0plus.h | 80 + .../TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h | 725 + .../TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h | 595 + .../TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct | 47 + .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 291 + .../TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h | 42 + .../TARGET_MPS2_M3/cmsis_nvic.c | 58 + .../TARGET_MPS2_M3/cmsis_nvic.h | 54 + .../TARGET_MPS2_M3/peripherallink.h | 53 + .../TARGET_MPS2_M3/system_CMSDK_CM3.c | 97 + .../TARGET_MPS2_M3/system_CMSDK_CM3.h | 80 + .../TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h | 1325 ++ .../TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h | 595 + .../TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct | 47 + .../TOOLCHAIN_ARM_STD/startup_MPS2.s | 293 + .../TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h | 42 + .../TARGET_MPS2_M4/cmsis_nvic.c | 58 + .../TARGET_MPS2_M4/cmsis_nvic.h | 54 + .../TARGET_MPS2_M4/peripherallink.h | 53 + .../TARGET_MPS2_M4/system_CMSDK_CM4.c | 101 + .../TARGET_MPS2_M4/system_CMSDK_CM4.h | 80 + .../TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h | 733 + .../TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h | 591 + .../TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct | 47 + .../TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s | 293 + .../TOOLCHAIN_GCC_ARM/gcc_arm.ld | 195 + .../TOOLCHAIN_GCC_ARM/startup_ARMCM7.s | 314 + .../TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis.h | 42 + .../TARGET_MPS2_M7/cmsis_nvic.c | 58 + .../TARGET_MPS2_M7/cmsis_nvic.h | 54 + .../TARGET_MPS2_M7/peripherallink.h | 53 + .../TARGET_MPS2_M7/system_CMSDK_CM7.c | 105 + .../TARGET_MPS2_M7/system_CMSDK_CM7.h | 80 + .../TOOLCHAIN_GCC_ARM/samd21j18a.ld | 126 + .../TOOLCHAIN_GCC_ARM/startup_samd21.c | 158 + .../TOOLCHAIN_IAR/startup_samd21.c | 173 + .../TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h | 13 + .../TARGET_SAMD21J18A/cmsis_nvic.c | 57 + .../TARGET_SAMD21J18A/cmsis_nvic.h | 51 + .../TARGET_SAMD21J18A/system_samd21.c | 34 + .../TARGET_SAMD21J18A/system_samd21.h | 19 + .../TOOLCHAIN_GCC_ARM/samr21g18a.ld | 126 + .../TOOLCHAIN_GCC_ARM/startup_samr21.c | 212 + .../TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h | 13 + .../TARGET_SAMR21G18A/cmsis_nvic.c | 58 + .../TARGET_SAMR21G18A/cmsis_nvic.h | 51 + .../TARGET_SAMR21G18A/system_samr21.c | 35 + .../TARGET_SAMR21G18A/system_samr21.h | 19 + .../cmsis/samd21/include/component/comp_ac.h | 516 + .../cmsis/samd21/include/component/comp_adc.h | 656 + .../cmsis/samd21/include/component/comp_dac.h | 243 + .../samd21/include/component/comp_dmac.h | 1043 ++ .../cmsis/samd21/include/component/comp_dsu.h | 508 + .../cmsis/samd21/include/component/comp_eic.h | 638 + .../samd21/include/component/comp_evsys.h | 561 + .../samd21/include/component/comp_gclk.h | 267 + .../samd21/include/component/comp_hmatrixb.h | 75 + .../cmsis/samd21/include/component/comp_i2s.h | 596 + .../cmsis/samd21/include/component/comp_mtb.h | 353 + .../samd21/include/component/comp_nvmctrl.h | 564 + .../cmsis/samd21/include/component/comp_pac.h | 61 + .../cmsis/samd21/include/component/comp_pm.h | 490 + .../samd21/include/component/comp_port.h | 352 + .../samd21/include/component/comp_rfctrl.h | 61 + .../cmsis/samd21/include/component/comp_rtc.h | 1019 ++ .../samd21/include/component/comp_sercom.h | 1465 ++ .../samd21/include/component/comp_sysctrl.h | 905 + .../cmsis/samd21/include/component/comp_tc.h | 641 + .../cmsis/samd21/include/component/comp_tcc.h | 1774 ++ .../cmsis/samd21/include/component/comp_usb.h | 1761 ++ .../cmsis/samd21/include/component/comp_wdt.h | 260 + .../cmsis/samd21/include/instance/ins_ac.h | 44 + .../cmsis/samd21/include/instance/ins_adc.h | 56 + .../cmsis/samd21/include/instance/ins_dac.h | 31 + .../cmsis/samd21/include/instance/ins_dmac.h | 66 + .../cmsis/samd21/include/instance/ins_dsu.h | 56 + .../cmsis/samd21/include/instance/ins_eic.h | 35 + .../cmsis/samd21/include/instance/ins_evsys.h | 154 + .../cmsis/samd21/include/instance/ins_gclk.h | 36 + .../cmsis/samd21/include/instance/ins_i2s.h | 51 + .../cmsis/samd21/include/instance/ins_mtb.h | 60 + .../samd21/include/instance/ins_nvmctrl.h | 49 + .../cmsis/samd21/include/instance/ins_pac0.h | 16 + .../cmsis/samd21/include/instance/ins_pac1.h | 16 + .../cmsis/samd21/include/instance/ins_pac2.h | 16 + .../cmsis/samd21/include/instance/ins_pm.h | 44 + .../cmsis/samd21/include/instance/ins_port.h | 93 + .../samd21/include/instance/ins_rfctrl.h | 14 + .../cmsis/samd21/include/instance/ins_rtc.h | 74 + .../samd21/include/instance/ins_sbmatrix.h | 122 + .../samd21/include/instance/ins_sercom0.h | 100 + .../samd21/include/instance/ins_sercom1.h | 100 + .../samd21/include/instance/ins_sercom2.h | 100 + .../samd21/include/instance/ins_sercom3.h | 100 + .../samd21/include/instance/ins_sercom4.h | 100 + .../samd21/include/instance/ins_sercom5.h | 100 + .../samd21/include/instance/ins_sysctrl.h | 77 + .../cmsis/samd21/include/instance/ins_tc3.h | 68 + .../cmsis/samd21/include/instance/ins_tc4.h | 68 + .../cmsis/samd21/include/instance/ins_tc5.h | 68 + .../cmsis/samd21/include/instance/ins_tc6.h | 68 + .../cmsis/samd21/include/instance/ins_tc7.h | 68 + .../cmsis/samd21/include/instance/ins_tcc0.h | 88 + .../cmsis/samd21/include/instance/ins_tcc1.h | 76 + .../cmsis/samd21/include/instance/ins_tcc2.h | 72 + .../cmsis/samd21/include/instance/ins_usb.h | 301 + .../cmsis/samd21/include/instance/ins_wdt.h | 28 + .../cmsis/samd21/include/pio/pio_samd21j18a.h | 1146 ++ .../cmsis/samd21/include/pio/pio_samr21g18a.h | 885 + .../utils/cmsis/samd21/include/samd21.h | 37 + .../utils/cmsis/samd21/include/samd21j18a.h | 532 + .../utils/cmsis/samd21/include/samr21.h | 25 + .../utils/cmsis/samd21/include/samr21g18a.h | 515 + .../TARGET_SAM21/utils/compiler.h | 1112 ++ .../TARGET_SAM21/utils/header_files/io.h | 34 + .../utils/preprocessor/mrecursion.h | 552 + .../TARGET_SAM21/utils/preprocessor/mrepeat.h | 292 + .../utils/preprocessor/preprocessor.h | 9 + .../TARGET_SAM21/utils/preprocessor/stringz.h | 38 + .../TARGET_SAM21/utils/preprocessor/tpaste.h | 57 + .../TARGET_SAM21/utils/status_codes.h | 109 + .../TARGET_K20XX/TARGET_K20D50M/MK20D5.h | 5836 +++++++ .../TOOLCHAIN_ARM_STD/MK20D5.sct | 14 + .../TOOLCHAIN_ARM_STD/startup_MK20D5.S | 412 + .../TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/MK20D5.ld | 163 + .../TOOLCHAIN_GCC_ARM/startup_MK20D5.S | 259 + .../TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf | 52 + .../TOOLCHAIN_IAR/startup_MK20D5.S | 271 + .../TARGET_K20XX/TARGET_K20D50M/cmsis.h | 13 + .../TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c | 55 + .../TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h | 51 + .../TARGET_K20D50M/system_MK20D5.c | 278 + .../TARGET_K20D50M/system_MK20D5.h | 87 + .../TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h | 6032 +++++++ .../TOOLCHAIN_ARM_STD/MK20DX256.sct | 13 + .../TOOLCHAIN_ARM_STD/startup_MK20DX256.S | 559 + .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/MK20DX256.ld | 164 + .../TOOLCHAIN_GCC_ARM/startup_MK20DX256.S | 366 + .../TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h | 13 + .../TARGET_TEENSY3_1/cmsis_nvic.c | 55 + .../TARGET_TEENSY3_1/cmsis_nvic.h | 51 + .../TARGET_TEENSY3_1/system_MK20DX256.c | 309 + .../TARGET_TEENSY3_1/system_MK20DX256.h | 85 + .../TARGET_Freescale/TARGET_K22F/MK22F51212.h | 10137 +++++++++++ .../TOOLCHAIN_ARM_STD/MK22F51212.sct | 13 + .../TOOLCHAIN_ARM_STD/startup_MK22F12.S | 679 + .../TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld | 164 + .../TOOLCHAIN_GCC_ARM/startup_MK22F12.S | 369 + .../TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf | 43 + .../TOOLCHAIN_IAR/startup_MK22F12.S | 535 + .../TARGET_Freescale/TARGET_K22F/cmsis.h | 13 + .../TARGET_Freescale/TARGET_K22F/cmsis_nvic.c | 55 + .../TARGET_Freescale/TARGET_K22F/cmsis_nvic.h | 51 + .../TARGET_K22F/system_MK22F51212.c | 395 + .../TARGET_K22F/system_MK22F51212.h | 367 + .../TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h | 3613 ++++ .../TOOLCHAIN_ARM_MICRO/MKL05Z4.sct | 12 + .../TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.S | 348 + .../TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/MKL05Z4.sct | 12 + .../TOOLCHAIN_ARM_STD/startup_MKL05Z4.S | 332 + .../TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_MKL05Z4.S | 225 + .../TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf | 43 + .../TOOLCHAIN_IAR/startup_MKL05Z4.S | 199 + .../TARGET_KLXX/TARGET_KL05Z/cmsis.h | 13 + .../TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c | 55 + .../TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h | 51 + .../TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c | 256 + .../TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h | 99 + .../TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h | 4155 +++++ .../TOOLCHAIN_ARM_MICRO/MKL25Z4.sct | 14 + .../TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S | 353 + .../TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/MKL25Z4.sct | 14 + .../TOOLCHAIN_ARM_STD/startup_MKL25Z4.S | 332 + .../TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld | 163 + .../TOOLCHAIN_GCC_ARM/startup_MKL25Z4.S | 239 + .../TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld | 197 + .../TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c | 147 + .../TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld | 153 + .../TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.S | 226 + .../TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf | 43 + .../TOOLCHAIN_IAR/startup_MKL25Z4.S | 213 + .../TARGET_KLXX/TARGET_KL25Z/cmsis.h | 13 + .../TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c | 55 + .../TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h | 51 + .../TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c | 300 + .../TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h | 84 + .../TARGET_KLXX/TARGET_KL26Z/MKL26Z4.h | 4454 +++++ .../TOOLCHAIN_ARM_MICRO/MKL26Z4.sct | 14 + .../TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s | 365 + .../TARGET_KL26Z/TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TARGET_KL26Z/TOOLCHAIN_GCC_ARM/MKL26Z4.ld | 163 + .../TOOLCHAIN_GCC_ARM/startup_MKL26Z4.S | 192 + .../TARGET_KL26Z/TOOLCHAIN_IAR/MKL26Z4.icf | 43 + .../TOOLCHAIN_IAR/startup_MKL26Z4.s | 251 + .../TARGET_KLXX/TARGET_KL26Z/cmsis.h | 13 + .../TARGET_KLXX/TARGET_KL26Z/cmsis_nvic.c | 55 + .../TARGET_KLXX/TARGET_KL26Z/cmsis_nvic.h | 51 + .../TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.c | 406 + .../TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h | 351 + .../TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h | 8856 ++++++++++ .../TOOLCHAIN_ARM_STD/MKL43Z4.sct | 14 + .../TOOLCHAIN_ARM_STD/startup_MKL43Z4.S | 362 + .../TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld | 163 + .../TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S | 243 + .../TARGET_KLXX/TARGET_KL43Z/cmsis.h | 13 + .../TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c | 30 + .../TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h | 26 + .../TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c | 224 + .../TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h | 335 + .../TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h | 5801 +++++++ .../TOOLCHAIN_ARM_STD/MKL46Z4.sct | 14 + .../TOOLCHAIN_ARM_STD/startup_MKL46Z4.S | 332 + .../TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld | 163 + .../TOOLCHAIN_GCC_ARM/startup_MKL46Z4.S | 241 + .../TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf | 43 + .../TOOLCHAIN_IAR/startup_MKL46Z4.S | 217 + .../TARGET_KLXX/TARGET_KL46Z/cmsis.h | 13 + .../TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c | 55 + .../TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h | 51 + .../TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c | 269 + .../TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h | 90 + .../TARGET_MCU_K64F/MK64F12.h | 14420 ++++++++++++++++ .../TOOLCHAIN_ARM_STD/MK64F.sct | 14 + .../TOOLCHAIN_ARM_STD/startup_MK64F12.S | 685 + .../TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld | 164 + .../TOOLCHAIN_GCC_ARM/startup_MK64F12.S | 369 + .../TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf | 49 + .../TOOLCHAIN_IAR/startup_MK64F12.S | 394 + .../TARGET_Freescale/TARGET_MCU_K64F/cmsis.h | 13 + .../TARGET_MCU_K64F/cmsis_nvic.c | 55 + .../TARGET_MCU_K64F/cmsis_nvic.h | 51 + .../TARGET_MCU_K64F/system_MK64F12.c | 391 + .../TARGET_MCU_K64F/system_MK64F12.h | 339 + .../TOOLCHAIN_ARM_STD/MAX32600.sct | 21 + .../TOOLCHAIN_ARM_STD/startup_MAX32600.S | 255 + .../TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp | 57 + .../TOOLCHAIN_GCC_ARM/max32600.ld | 182 + .../TOOLCHAIN_GCC_ARM/startup_max32600.S | 262 + .../TOOLCHAIN_IAR/MAX32600.icf | 29 + .../TOOLCHAIN_IAR/startup_MAX32600.S | 383 + .../TARGET_Maxim/TARGET_MAX32600/adc_regs.h | 466 + .../TARGET_Maxim/TARGET_MAX32600/aes_regs.h | 159 + .../TARGET_Maxim/TARGET_MAX32600/afe_regs.h | 626 + .../TARGET_MAX32600/clkman_regs.h | 493 + .../TARGET_Maxim/TARGET_MAX32600/cmsis.h | 40 + .../TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c | 65 + .../TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h | 53 + .../TARGET_Maxim/TARGET_MAX32600/crc_regs.h | 89 + .../TARGET_Maxim/TARGET_MAX32600/dac_regs.h | 180 + .../TARGET_Maxim/TARGET_MAX32600/flc_regs.h | 210 + .../TARGET_Maxim/TARGET_MAX32600/gpio_regs.h | 477 + .../TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h | 192 + .../TARGET_Maxim/TARGET_MAX32600/icc_regs.h | 96 + .../TARGET_Maxim/TARGET_MAX32600/ioman_regs.h | 508 + .../TARGET_Maxim/TARGET_MAX32600/lcd_regs.h | 70 + .../TARGET_Maxim/TARGET_MAX32600/maa_regs.h | 124 + .../TARGET_Maxim/TARGET_MAX32600/max32600.h | 666 + .../TARGET_Maxim/TARGET_MAX32600/pmu_regs.h | 111 + .../TARGET_Maxim/TARGET_MAX32600/pt_regs.h | 175 + .../TARGET_MAX32600/pwrman_regs.h | 386 + .../TARGET_MAX32600/pwrseq_regs.h | 299 + .../TARGET_Maxim/TARGET_MAX32600/rtc_regs.h | 246 + .../TARGET_Maxim/TARGET_MAX32600/spi_regs.h | 215 + .../TARGET_MAX32600/system_max32600.c | 197 + .../TARGET_MAX32600/system_max32600.h | 53 + .../TARGET_Maxim/TARGET_MAX32600/tmr_regs.h | 146 + .../TARGET_Maxim/TARGET_MAX32600/tpu_regs.h | 108 + .../TARGET_Maxim/TARGET_MAX32600/trim_regs.h | 92 + .../TARGET_Maxim/TARGET_MAX32600/uart_regs.h | 175 + .../TARGET_Maxim/TARGET_MAX32600/usb_regs.h | 480 + .../TARGET_Maxim/TARGET_MAX32600/wdt_regs.h | 150 + .../TOOLCHAIN_ARM_STD/MAX32610.sct | 21 + .../TOOLCHAIN_ARM_STD/startup_MAX32610.S | 255 + .../TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp | 57 + .../TOOLCHAIN_GCC_ARM/max32610.ld | 182 + .../TOOLCHAIN_GCC_ARM/startup_max32610.S | 262 + .../TOOLCHAIN_IAR/MAX32610.icf | 29 + .../TOOLCHAIN_IAR/startup_MAX32610.S | 383 + .../TARGET_Maxim/TARGET_MAX32610/adc_regs.h | 466 + .../TARGET_Maxim/TARGET_MAX32610/aes_regs.h | 159 + .../TARGET_Maxim/TARGET_MAX32610/afe_regs.h | 626 + .../TARGET_MAX32610/clkman_regs.h | 493 + .../TARGET_Maxim/TARGET_MAX32610/cmsis.h | 40 + .../TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c | 65 + .../TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h | 53 + .../TARGET_Maxim/TARGET_MAX32610/crc_regs.h | 89 + .../TARGET_Maxim/TARGET_MAX32610/dac_regs.h | 180 + .../TARGET_Maxim/TARGET_MAX32610/flc_regs.h | 210 + .../TARGET_Maxim/TARGET_MAX32610/gpio_regs.h | 477 + .../TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h | 192 + .../TARGET_Maxim/TARGET_MAX32610/icc_regs.h | 96 + .../TARGET_Maxim/TARGET_MAX32610/ioman_regs.h | 508 + .../TARGET_Maxim/TARGET_MAX32610/maa_regs.h | 124 + .../TARGET_Maxim/TARGET_MAX32610/max32610.h | 655 + .../TARGET_Maxim/TARGET_MAX32610/pmu_regs.h | 111 + .../TARGET_Maxim/TARGET_MAX32610/pt_regs.h | 175 + .../TARGET_MAX32610/pwrman_regs.h | 386 + .../TARGET_MAX32610/pwrseq_regs.h | 299 + .../TARGET_Maxim/TARGET_MAX32610/rtc_regs.h | 246 + .../TARGET_Maxim/TARGET_MAX32610/spi_regs.h | 215 + .../TARGET_MAX32610/system_max32610.c | 200 + .../TARGET_MAX32610/system_max32610.h | 53 + .../TARGET_Maxim/TARGET_MAX32610/tmr_regs.h | 146 + .../TARGET_Maxim/TARGET_MAX32610/tpu_regs.h | 108 + .../TARGET_Maxim/TARGET_MAX32610/trim_regs.h | 92 + .../TARGET_Maxim/TARGET_MAX32610/uart_regs.h | 175 + .../TARGET_Maxim/TARGET_MAX32610/usb_regs.h | 453 + .../TARGET_Maxim/TARGET_MAX32610/wdt_regs.h | 150 + .../TARGET_MCU_NORDIC_16K/startup_nRF51822.S | 187 + .../TARGET_MCU_NORDIC_32K/nRF51822.sct | 24 + .../TARGET_MCU_NORDIC_32K/startup_nRF51822.S | 196 + .../TARGET_MCU_NRF51_16K_S110/nRF51822.sct | 24 + .../TARGET_MCU_NRF51_16K_S130/nRF51822.sct | 24 + .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_MCU_NORDIC_32K/NRF51822.ld | 151 + .../TARGET_MCU_NRF51_16K_S110/NRF51822.ld | 151 + .../TARGET_MCU_NRF51_16K_S130/NRF51822.ld | 151 + .../TOOLCHAIN_GCC_ARM/startup_NRF51822.S | 262 + .../TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf | 43 + .../startup_NRF51822_IAR.S | 237 + .../TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf | 44 + .../startup_NRF51822_IAR.S | 237 + .../s110_nrf51822_7.1.0_softdevice.bin | Bin 0 -> 86540 bytes .../TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h | 13 + .../TARGET_MCU_NRF51822/cmsis_nvic.c | 103 + .../TARGET_MCU_NRF51822/cmsis_nvic.h | 53 + .../compiler_abstraction.h | 109 + .../TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h | 48 + .../TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h | 1312 ++ .../TARGET_MCU_NRF51822/nrf51_bitfields.h | 7135 ++++++++ .../TARGET_MCU_NRF51822/nrf_delay.h | 74 + .../TARGET_MCU_NRF51822/system_nrf51.c | 135 + .../TARGET_MCU_NRF51822/system_nrf51.h | 68 + .../TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h | 1247 ++ .../TARGET_LPC11U68/LPC11U68.sct | 13 + .../TARGET_LPC11U68/startup_LPC11U6x.S | 244 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TARGET_LPC11U68/LPC11U68.sct | 13 + .../TARGET_LPC11U68/startup_LPC11U6x.S | 244 + .../TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_LPC11U68/LPC11U68.ld | 235 + .../TARGET_LPC11U68/startup_LPC11U68.cpp | 181 + .../TARGET_LPC11U68/LPC11U68.ld | 237 + .../TARGET_LPC11U68/aeabi_romdiv_patch.S | 93 + .../TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c | 85 + .../TARGET_LPC11U68/startup_LPC11U68.cpp | 201 + .../TARGET_LPC11U68/LPC11U68.icf | 47 + .../TARGET_LPC11U68/startup_LPC11U6X.S | 251 + .../cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c | 55 + .../TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h | 51 + .../TARGET_LPC11U6X/system_LPC11U6x.c | 574 + .../TARGET_LPC11U6X/system_LPC11U6x.h | 64 + .../TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h | 670 + .../LPC11U34.sct | 17 + .../startup_LPC11xx.S | 325 + .../TARGET_LPC11U24_301/LPC11U24.sct | 17 + .../TARGET_LPC11U24_301/startup_LPC11xx.S | 325 + .../TARGET_LPC11U24_401/LPC11U24.sct | 17 + .../TARGET_LPC11U24_401/startup_LPC11xx.S | 325 + .../TARGET_LPC11U34_421/LPC11U34.sct | 17 + .../TARGET_LPC11U34_421/startup_LPC11xx.S | 325 + .../TARGET_LPC11U35_401/LPC11U35.sct | 17 + .../TARGET_LPC11U35_401/startup_LPC11xx.S | 325 + .../TARGET_LPC11U37H_401/LPC11U37.sct | 20 + .../TARGET_LPC11U37H_401/startup_LPC11xx.S | 325 + .../TARGET_LPC11U37_501/LPC11U37.sct | 20 + .../TARGET_LPC11U37_501/startup_LPC11xx.S | 325 + .../TARGET_MCU_LPC11U35_501/LPC11U35.sct | 20 + .../TARGET_MCU_LPC11U35_501/startup_LPC11xx.S | 325 + .../TARGET_OC_MBUINO/LPC11U24.sct | 17 + .../TARGET_OC_MBUINO/startup_LPC11xx.S | 325 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../LPC11U34.sct | 17 + .../startup_LPC11xx.S | 308 + .../TARGET_LPC11U24_301/LPC11U24.sct | 17 + .../TARGET_LPC11U24_301/startup_LPC11xx.S | 308 + .../TARGET_LPC11U24_401/LPC11U24.sct | 17 + .../TARGET_LPC11U24_401/startup_LPC11xx.S | 308 + .../TARGET_LPC11U34_421/LPC11U34.sct | 17 + .../TARGET_LPC11U34_421/startup_LPC11xx.S | 308 + .../TARGET_LPC11U35_401/LPC11U35.sct | 17 + .../TARGET_LPC11U35_401/startup_LPC11xx.S | 308 + .../TARGET_LPC11U35_501/LPC11U35.sct | 20 + .../TARGET_LPC11U35_501/startup_LPC11xx.S | 308 + .../TARGET_LPC11U37H_401/LPC11U37.sct | 20 + .../TARGET_LPC11U37H_401/startup_LPC11xx.S | 308 + .../TARGET_LPC11U37_501/LPC11U37.sct | 20 + .../TARGET_LPC11U37_501/startup_LPC11xx.S | 308 + .../TARGET_OC_MBUINO/LPC11U24.sct | 17 + .../TARGET_OC_MBUINO/startup_LPC11xx.S | 308 + .../TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../LPC11U34.ld | 151 + .../TARGET_LPC11U24_301/LPC11U24.ld | 154 + .../TARGET_LPC11U24_401/LPC11U24.ld | 154 + .../TARGET_LPC11U34_421/LPC11U34.ld | 151 + .../TARGET_LPC11U35_401/LPC11U35.ld | 151 + .../TARGET_LPC11U35_501/LPC11U35.ld | 151 + .../TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld | 151 + .../TARGET_LPC11U37H_401/LPC11U37.ld | 152 + .../TARGET_LPC11U37_501/LPC11U37.ld | 151 + .../TARGET_LPCCAPPUCCINO/LPC11U37.ld | 151 + .../TARGET_OC_MBUINO/LPC11U24.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_LPC11xx.S | 218 + .../TARGET_LPC11U24/LPC11U24.ld | 153 + .../TARGET_LPC11U35_401/LPC11U35.ld | 155 + .../TARGET_LPC11U35_501/LPC11U35.ld | 155 + .../TARGET_LPC11U37H_401/LPC11U37.ld | 157 + .../TARGET_LPC11U37_501/LPC11U37.ld | 155 + .../TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp | 167 + .../TOOLCHAIN_GCC_CS/LPC11U24.ld | 207 + .../TOOLCHAIN_GCC_CS/startup_LPC11xx.S | 112 + .../TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/sys.cpp | 79 + .../TARGET_LPC11U24_301/LPC11U24.icf | 41 + .../TARGET_LPC11U24_301/startup_LPC11xx.S | 333 + .../TARGET_LPC11U24_401/LPC11U24.icf | 41 + .../TARGET_LPC11U24_401/startup_LPC11xx.S | 333 + .../TARGET_LPC11U35_401/LPC11U35.icf | 41 + .../TARGET_LPC11U35_401/startup_LPC11xx.S | 333 + .../TARGET_LPC11U35_501/LPC11U35.icf | 46 + .../TARGET_LPC11U35_501/startup_LPC11xx.S | 333 + .../TARGET_LPC11U37_501/LPC11U37.icf | 46 + .../TARGET_LPC11U37_501/startup_LPC11xx.S | 333 + .../TARGET_OC_MBUINO/LPC11U24.icf | 41 + .../TARGET_OC_MBUINO/startup_LPC11xx.S | 333 + .../cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c | 81 + .../TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h | 51 + .../TARGET_NXP/TARGET_LPC11UXX/power_api.h | 82 + .../TARGET_LPC11UXX/system_LPC11Uxx.c | 450 + .../TARGET_LPC11UXX/system_LPC11Uxx.h | 64 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h | 602 + .../TARGET_LPC11CXX/system_LPC11xx.c | 367 + .../TARGET_LPC11XX/system_LPC11xx.c | 367 + .../TARGET_LPC11CXX/LPC11C24.sct | 16 + .../TARGET_LPC11CXX/startup_LPC11xx.S | 304 + .../TARGET_LPC11XX/LPC1114.sct | 16 + .../TARGET_LPC11XX/startup_LPC11xx.S | 304 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TARGET_LPC11CXX/LPC11C24.sct | 14 + .../TARGET_LPC11CXX/startup_LPC11xx.S | 292 + .../TARGET_LPC11XX/LPC1114.sct | 14 + .../TARGET_LPC11XX/startup_LPC11xx.S | 292 + .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TARGET_LPC11CXX/LPC11C24.ld | 149 + .../TARGET_LPC11XX/LPC1114.ld | 149 + .../TOOLCHAIN_GCC_ARM/startup_LPC11xx.S | 216 + .../TARGET_LPC11XX/LPC1114.ld | 135 + .../TARGET_LPC11XX/startup_LPC11xx.cpp | 167 + .../TOOLCHAIN_GCC_CS/startup_LPC11xx.S | 112 + .../TOOLCHAIN_GCC_CS/sys.cpp | 79 + .../TARGET_LPC11CXX/LPC11C24.icf | 36 + .../TARGET_LPC11CXX/startup_LPC11xx.S | 299 + .../TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf | 36 + .../TARGET_LPC11XX/startup_LPC11xx.S | 299 + .../TARGET_LPC11XX_11CXX/bitfields.h | 1768 ++ .../TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h | 14 + .../TARGET_LPC11XX_11CXX/cmsis_nvic.c | 82 + .../TARGET_LPC11XX_11CXX/cmsis_nvic.h | 51 + .../TARGET_LPC11XX_11CXX/system_LPC11xx.h | 64 + .../TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h | 776 + .../TOOLCHAIN_ARM_MICRO/LPC1347.sct | 19 + .../TOOLCHAIN_ARM_MICRO/startup_LPC13xx.S | 231 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/LPC1347.sct | 19 + .../TOOLCHAIN_ARM_STD/startup_LPC13xx.S | 215 + .../TARGET_LPC13XX/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/LPC1347.ld | 149 + .../TOOLCHAIN_GCC_ARM/startup_LPC13xx.S | 213 + .../TARGET_LPC13XX/TOOLCHAIN_IAR/LPC1347.icf | 47 + .../TOOLCHAIN_IAR/startup_LPC1347.S | 178 + .../cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c | 56 + .../TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h | 51 + .../TARGET_LPC13XX/system_LPC13Uxx.c | 437 + .../TARGET_LPC13XX/system_LPC13Uxx.h | 64 + .../cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h | 1725 ++ .../TOOLCHAIN_ARM_MICRO/LPC15xx.sct | 13 + .../TOOLCHAIN_ARM_MICRO/startup_LPC15xx.S | 317 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/LPC1549.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_LPC15xx.S | 247 + .../TOOLCHAIN_GCC_CR/LPC1549.ld | 214 + .../TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp | 219 + .../TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf | 37 + .../TOOLCHAIN_IAR/startup_LPC15xx.S | 274 + .../cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c | 55 + .../TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h | 51 + .../TARGET_LPC15XX/system_LPC15xx.c | 517 + .../TARGET_LPC15XX/system_LPC15xx.h | 72 + .../cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h | 1035 ++ .../TOOLCHAIN_ARM_MICRO/LPC1768.sct | 22 + .../TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S | 243 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/LPC1768.sct | 22 + .../TOOLCHAIN_ARM_STD/startup_LPC17xx.S | 226 + .../TARGET_LPC176X/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/LPC1768.ld | 172 + .../TARGET_XBED_LPC1768/XBED_LPC1768.ld | 172 + .../TOOLCHAIN_GCC_ARM/startup_LPC17xx.S | 223 + .../TOOLCHAIN_GCC_CR/LPC1768.ld | 154 + .../TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp | 183 + .../TOOLCHAIN_GCC_CS/LPC1768.ld | 212 + .../TOOLCHAIN_GCC_CS/startup_LPC17xx.S | 204 + .../TARGET_LPC176X/TOOLCHAIN_GCC_CS/sys.cpp | 80 + .../TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf | 45 + .../TOOLCHAIN_IAR/startup_LPC17xx.S | 375 + .../cmsis/TARGET_NXP/TARGET_LPC176X/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c | 56 + .../TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h | 51 + .../TARGET_LPC176X/system_LPC17xx.c | 584 + .../TARGET_LPC176X/system_LPC17xx.h | 60 + .../cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h | 864 + .../TOOLCHAIN_ARM_MICRO/LPC2368.sct | 24 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_MICRO/vector_functions.S | 248 + .../TOOLCHAIN_ARM_MICRO/vector_table.S | 99 + .../TOOLCHAIN_ARM_STD/LPC2368.sct | 24 + .../TARGET_LPC23XX/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/vector_functions.S | 248 + .../TOOLCHAIN_ARM_STD/vector_table.S | 99 + .../TOOLCHAIN_GCC_ARM/LPC2368.ld | 208 + .../TOOLCHAIN_GCC_ARM/vector_functions.S | 148 + .../TOOLCHAIN_GCC_ARM/vector_table.S | 45 + .../TOOLCHAIN_GCC_CR/LPC2368.ld | 210 + .../TOOLCHAIN_GCC_CR/vector_functions.S | 149 + .../TOOLCHAIN_GCC_CR/vector_table.S | 45 + .../TOOLCHAIN_GCC_CS/LPC2368.ld | 207 + .../TOOLCHAIN_GCC_CS/vector_functions.S | 180 + .../TOOLCHAIN_GCC_CS/vector_table.S | 45 + .../cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.c | 40 + .../TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h | 51 + .../TARGET_NXP/TARGET_LPC23XX/core_arm7.c | 44 + .../TARGET_NXP/TARGET_LPC23XX/core_arm7.h | 276 + .../TARGET_LPC23XX/system_LPC23xx.c | 144 + .../TARGET_LPC23XX/system_LPC23xx.h | 44 + .../TARGET_NXP/TARGET_LPC23XX/vector_defns.h | 77 + .../TARGET_LPC23XX/vector_realmonitor.c | 22 + .../cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h | 972 ++ .../TOOLCHAIN_GCC_ARM/LPC2460.ld | 210 + .../TOOLCHAIN_GCC_ARM/vector_functions.S | 195 + .../TOOLCHAIN_GCC_ARM/vector_table.S | 45 + .../cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c | 40 + .../TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h | 51 + .../TARGET_NXP/TARGET_LPC2460/core_arm7.c | 44 + .../TARGET_NXP/TARGET_LPC2460/core_arm7.h | 343 + .../TARGET_LPC2460/system_LPC24xx.c | 164 + .../TARGET_LPC2460/system_LPC24xx.h | 44 + .../TARGET_NXP/TARGET_LPC2460/vector_defns.h | 77 + .../TARGET_LPC2460/vector_realmonitor.c | 22 + .../TARGET_LPC408X/LPC407x_8x_177x_8x.h | 1523 ++ .../TOOLCHAIN_ARM_STD/LPC407X_8X.sct | 31 + .../startup_LPC407x_8x_177x_8x.S | 254 + .../TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp | 32 + .../TOOLCHAIN_ARM_STD/sys_helper.cpp | 19 + .../TOOLCHAIN_ARM_STD/sys_helper.h | 16 + .../TOOLCHAIN_GCC_ARM/LPC4088.ld | 172 + .../TOOLCHAIN_GCC_ARM/startup_LPC408x.S | 235 + .../TOOLCHAIN_GCC_CR/LPC407x_8x.ld | 181 + .../TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp | 438 + .../TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf | 42 + .../TOOLCHAIN_IAR/startup_LPC408x.S | 256 + .../cmsis/TARGET_NXP/TARGET_LPC408X/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC408X/cmsis_nvic.c | 56 + .../TARGET_NXP/TARGET_LPC408X/cmsis_nvic.h | 51 + .../system_LPC407x_8x_177x_8x.c | 571 + .../system_LPC407x_8x_177x_8x.h | 89 + .../cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h | 2113 +++ .../TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini | 12 + .../TARGET_LPC4330/LPC43xx.sct | 25 + .../TARGET_LPC4330/startup_LPC43xx.S | 294 + .../TARGET_LPC4337/LPC4337.sct | 22 + .../TARGET_LPC4337/startup_LPC4337.S | 291 + .../TARGET_LPC43XX/TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/LPC4330.ld | 174 + .../TOOLCHAIN_GCC_ARM/startup_LPC43xx.S | 260 + .../TOOLCHAIN_GCC_CR/LPC43xx.ld | 281 + .../TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp | 500 + .../TARGET_LPC43XX/TOOLCHAIN_IAR/LPC43xx.icf | 36 + .../TOOLCHAIN_IAR/startup_LPC43xx.S | 292 + .../cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis.h | 15 + .../TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.c | 61 + .../TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.h | 51 + .../TARGET_LPC43XX/system_LPC43xx.c | 373 + .../TARGET_LPC43XX/system_LPC43xx.h | 90 + .../cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h | 710 + .../TOOLCHAIN_ARM_MICRO/LPC810.sct | 14 + .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 211 + .../TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf | 36 + .../TOOLCHAIN_IAR/startup_LPC8xx.S | 197 + .../TARGET_LPC810/system_LPC8xx.c | 372 + .../TOOLCHAIN_ARM_MICRO/LPC812.sct | 14 + .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 211 + .../TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf | 36 + .../TOOLCHAIN_IAR/startup_LPC8xx.S | 198 + .../TARGET_LPC812/system_LPC8xx.c | 381 + .../TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c | 55 + .../TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h | 51 + .../TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h | 63 + .../cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h | 1308 ++ .../TOOLCHAIN_ARM_MICRO/LPC824.sct | 14 + .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 218 + .../TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld | 152 + .../TOOLCHAIN_GCC_ARM/startup_LPC824.S | 228 + .../TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld | 199 + .../TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp | 351 + .../TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf | 36 + .../TOOLCHAIN_IAR/startup_LPC8xx.S | 216 + .../TARGET_LPC824/system_LPC8xx.c | 389 + .../TOOLCHAIN_ARM_MICRO/LPC824.sct | 14 + .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 218 + .../TOOLCHAIN_GCC_ARM/LPC824.ld | 152 + .../TOOLCHAIN_GCC_ARM/startup_LPC824.S | 228 + .../TARGET_SSCI824/system_LPC8xx.c | 389 + .../TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h | 13 + .../TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c | 55 + .../TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h | 51 + .../TARGET_NXP/TARGET_LPC82X/system_LPC82x.h | 63 + .../TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h | 1057 ++ .../TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c | 135 + .../TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h | 71 + .../TOOLCHAIN_ARM_STD/MBRZA1H.sct | 43 + .../TOOLCHAIN_ARM_STD/startup_MBRZA1H.S | 454 + .../TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld | 227 + .../TOOLCHAIN_GCC_ARM/startup_RZ1AH.S | 532 + .../TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h | 12 + .../TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c | 42 + .../TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h | 46 + .../TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h | 85 + .../cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c | 305 + .../cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h | 316 + .../inc/iobitmasks/bsc_iobitmask.h | 357 + .../inc/iobitmasks/cpg_iobitmask.h | 461 + .../inc/iobitmasks/dmac_iobitmask.h | 2675 +++ .../inc/iobitmasks/gpio_iobitmask.h | 5793 +++++++ .../inc/iobitmasks/intc_iobitmask.h | 11236 ++++++++++++ .../inc/iobitmasks/mtu2_iobitmask.h | 462 + .../inc/iobitmasks/ostm_iobitmask.h | 123 + .../inc/iobitmasks/riic_iobitmask.h | 231 + .../inc/iobitmasks/rspi_iobitmask.h | 215 + .../inc/iobitmasks/scif_iobitmask.h | 1065 ++ .../inc/iobitmasks/usb_iobitmask.h | 731 + .../TARGET_RZ_A1H/inc/iodefine.h | 136 + .../inc/iodefines/adc_iodefine.h | 98 + .../inc/iodefines/bsc_iodefine.h | 99 + .../inc/iodefines/ceu_iodefine.h | 269 + .../inc/iodefines/cpg_iodefine.h | 239 + .../inc/iodefines/disc_iodefine.h | 93 + .../inc/iodefines/dmac_iodefine.h | 733 + .../inc/iodefines/dvdec_iodefine.h | 391 + .../inc/iodefines/ether_iodefine.h | 427 + .../inc/iodefines/flctl_iodefine.h | 72 + .../inc/iodefines/gpio_iodefine.h | 1074 ++ .../inc/iodefines/ieb_iodefine.h | 119 + .../inc/iodefines/inb_iodefine.h | 92 + .../inc/iodefines/intc_iodefine.h | 1026 ++ .../inc/iodefines/irda_iodefine.h | 42 + .../inc/iodefines/jcu_iodefine.h | 169 + .../inc/iodefines/l2c_iodefine.h | 195 + .../inc/iodefines/lin_iodefine.h | 174 + .../inc/iodefines/lvds_iodefine.h | 54 + .../inc/iodefines/mlb_iodefine.h | 498 + .../inc/iodefines/mmc_iodefine.h | 92 + .../inc/iodefines/mtu2_iodefine.h | 217 + .../inc/iodefines/ostm_iodefine.h | 78 + .../inc/iodefines/pfv_iodefine.h | 150 + .../inc/iodefines/pwm_iodefine.h | 135 + .../inc/iodefines/riic_iodefine.h | 556 + .../inc/iodefines/romdec_iodefine.h | 166 + .../inc/iodefines/rscan0_iodefine.h | 9038 ++++++++++ .../inc/iodefines/rspi_iodefine.h | 204 + .../inc/iodefines/rtc_iodefine.h | 102 + .../inc/iodefines/scif_iodefine.h | 182 + .../inc/iodefines/scim_iodefine.h | 87 + .../inc/iodefines/scux_iodefine.h | 808 + .../inc/iodefines/sdg_iodefine.h | 86 + .../inc/iodefines/spdif_iodefine.h | 68 + .../inc/iodefines/spibsc_iodefine.h | 173 + .../inc/iodefines/ssif_iodefine.h | 131 + .../inc/iodefines/usb20_iodefine.h | 546 + .../inc/iodefines/vdc5_iodefine.h | 1596 ++ .../inc/iodefines/wdt_iodefine.h | 46 + .../TARGET_RZ_A1H/inc/reg32_t.h | 11 + .../TARGET_RZ_A1H/inc/rza_io_regrw.h | 83 + .../TARGET_RZ_A1H/mbed_sf_boot.c | 826 + .../TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c | 192 + .../TARGET_RZ_A1H/nvic_wrapper.c | 229 + .../TARGET_RZ_A1H/nvic_wrapper.h | 84 + .../TARGET_RENESAS/TARGET_RZ_A1H/pl310.c | 128 + .../TARGET_RENESAS/TARGET_RZ_A1H/pl310.h | 114 + .../TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h | 61 + .../TARGET_RZ_A1H/rza_io_regrw.c | 200 + .../TARGET_RZ_A1H/system_MBRZA1H.c | 384 + .../TARGET_RZ_A1H/system_MBRZA1H.h | 65 + .../Release_Notes_stm32f0xx_hal.html | 846 + .../TOOLCHAIN_GCC_ARM/STM32F0xx.ld | 155 + .../TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S | 299 + .../TARGET_DISCO_F051R8/cmsis.h | 38 + .../TARGET_DISCO_F051R8/cmsis_nvic.c | 61 + .../TARGET_DISCO_F051R8/cmsis_nvic.h | 55 + .../TARGET_DISCO_F051R8/stm32f051x8.h | 3815 ++++ .../TARGET_DISCO_F051R8/stm32f0xx.h | 228 + .../TARGET_DISCO_F051R8/system_stm32f0xx.c | 435 + .../TARGET_DISCO_F051R8/system_stm32f0xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S | 216 + .../TOOLCHAIN_ARM_MICRO/stm32f0xx.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f030x8.S | 189 + .../TOOLCHAIN_ARM_STD/stm32f0xx.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F030X8.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S | 288 + .../TOOLCHAIN_IAR/startup_stm32f030x8.S | 291 + .../TOOLCHAIN_IAR/stm32f030x8.icf | 31 + .../TARGET_NUCLEO_F030R8/cmsis.h | 38 + .../TARGET_NUCLEO_F030R8/cmsis_nvic.c | 61 + .../TARGET_NUCLEO_F030R8/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F030R8/hal_tick.c | 159 + .../TARGET_NUCLEO_F030R8/hal_tick.h | 62 + .../TARGET_NUCLEO_F030R8/stm32f030x8.h | 3214 ++++ .../TARGET_NUCLEO_F030R8/stm32f0xx.h | 237 + .../TARGET_NUCLEO_F030R8/system_stm32f0xx.c | 450 + .../TARGET_NUCLEO_F030R8/system_stm32f0xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S | 239 + .../TOOLCHAIN_ARM_MICRO/stm32f070xb.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f070xb.S | 212 + .../TOOLCHAIN_ARM_STD/stm32f070xb.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F070XB.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S | 297 + .../TOOLCHAIN_IAR/startup_stm32f070xb.S | 305 + .../TOOLCHAIN_IAR/stm32f070xb.icf | 31 + .../TARGET_NUCLEO_F070RB/cmsis.h | 38 + .../TARGET_NUCLEO_F070RB/cmsis_nvic.c | 61 + .../TARGET_NUCLEO_F070RB/cmsis_nvic.h | 54 + .../TARGET_NUCLEO_F070RB/hal_tick.c | 167 + .../TARGET_NUCLEO_F070RB/hal_tick.h | 61 + .../TARGET_NUCLEO_F070RB/stm32f070xb.h | 3420 ++++ .../TARGET_NUCLEO_F070RB/stm32f0xx.h | 237 + .../TARGET_NUCLEO_F070RB/system_stm32f0xx.c | 467 + .../TARGET_NUCLEO_F070RB/system_stm32f0xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S | 247 + .../TOOLCHAIN_ARM_MICRO/stm32f072rb.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f072xb.S | 220 + .../TOOLCHAIN_ARM_STD/stm32f072rb.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F072XB.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S | 315 + .../TOOLCHAIN_IAR/startup_stm32f072xb.S | 325 + .../TOOLCHAIN_IAR/stm32f072xb.icf | 30 + .../TARGET_NUCLEO_F072RB/cmsis.h | 38 + .../TARGET_NUCLEO_F072RB/cmsis_nvic.c | 61 + .../TARGET_NUCLEO_F072RB/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F072RB/hal_tick.c | 123 + .../TARGET_NUCLEO_F072RB/hal_tick.h | 60 + .../TARGET_NUCLEO_F072RB/stm32f072xb.h | 5576 ++++++ .../TARGET_NUCLEO_F072RB/stm32f0xx.h | 237 + .../TARGET_NUCLEO_F072RB/system_stm32f0xx.c | 467 + .../TARGET_NUCLEO_F072RB/system_stm32f0xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S | 244 + .../TOOLCHAIN_ARM_MICRO/stm32f091rc.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f091rc.S | 217 + .../TOOLCHAIN_ARM_STD/stm32f091rc.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F091XC.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S | 311 + .../TOOLCHAIN_IAR/startup_stm32f091xc.S | 319 + .../TOOLCHAIN_IAR/stm32f091xc.icf | 31 + .../TARGET_NUCLEO_F091RC/cmsis.h | 38 + .../TARGET_NUCLEO_F091RC/cmsis_nvic.c | 61 + .../TARGET_NUCLEO_F091RC/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F091RC/hal_tick.c | 123 + .../TARGET_NUCLEO_F091RC/hal_tick.h | 60 + .../TARGET_NUCLEO_F091RC/stm32f091xc.h | 5710 ++++++ .../TARGET_NUCLEO_F091RC/stm32f0xx.h | 237 + .../TARGET_NUCLEO_F091RC/system_stm32f0xx.c | 467 + .../TARGET_NUCLEO_F091RC/system_stm32f0xx.h | 123 + .../TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c | 430 + .../TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h | 697 + .../TARGET_STM32F0/stm32f0xx_hal_adc.c | 1865 ++ .../TARGET_STM32F0/stm32f0xx_hal_adc.h | 951 + .../TARGET_STM32F0/stm32f0xx_hal_adc_ex.c | 265 + .../TARGET_STM32F0/stm32f0xx_hal_adc_ex.h | 98 + .../TARGET_STM32F0/stm32f0xx_hal_can.c | 1400 ++ .../TARGET_STM32F0/stm32f0xx_hal_can.h | 810 + .../TARGET_STM32F0/stm32f0xx_hal_cec.c | 1119 ++ .../TARGET_STM32F0/stm32f0xx_hal_cec.h | 598 + .../TARGET_STM32F0/stm32f0xx_hal_comp.c | 695 + .../TARGET_STM32F0/stm32f0xx_hal_comp.h | 479 + .../TARGET_STM32F0/stm32f0xx_hal_conf.h | 307 + .../TARGET_STM32F0/stm32f0xx_hal_cortex.c | 342 + .../TARGET_STM32F0/stm32f0xx_hal_cortex.h | 166 + .../TARGET_STM32F0/stm32f0xx_hal_crc.c | 506 + .../TARGET_STM32F0/stm32f0xx_hal_crc.h | 327 + .../TARGET_STM32F0/stm32f0xx_hal_crc_ex.c | 275 + .../TARGET_STM32F0/stm32f0xx_hal_crc_ex.h | 202 + .../TARGET_STM32F0/stm32f0xx_hal_dac.c | 693 + .../TARGET_STM32F0/stm32f0xx_hal_dac.h | 354 + .../TARGET_STM32F0/stm32f0xx_hal_dac_ex.c | 1083 ++ .../TARGET_STM32F0/stm32f0xx_hal_dac_ex.h | 297 + .../TARGET_STM32F0/stm32f0xx_hal_def.h | 183 + .../TARGET_STM32F0/stm32f0xx_hal_dma.c | 703 + .../TARGET_STM32F0/stm32f0xx_hal_dma.h | 459 + .../TARGET_STM32F0/stm32f0xx_hal_dma_ex.h | 783 + .../TARGET_STM32F0/stm32f0xx_hal_flash.c | 722 + .../TARGET_STM32F0/stm32f0xx_hal_flash.h | 515 + .../TARGET_STM32F0/stm32f0xx_hal_flash_ex.c | 854 + .../TARGET_STM32F0/stm32f0xx_hal_flash_ex.h | 296 + .../TARGET_STM32F0/stm32f0xx_hal_gpio.c | 561 + .../TARGET_STM32F0/stm32f0xx_hal_gpio.h | 318 + .../TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h | 810 + .../TARGET_STM32F0/stm32f0xx_hal_i2c.c | 4101 +++++ .../TARGET_STM32F0/stm32f0xx_hal_i2c.h | 562 + .../TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c | 292 + .../TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h | 132 + .../TARGET_STM32F0/stm32f0xx_hal_i2s.c | 1389 ++ .../TARGET_STM32F0/stm32f0xx_hal_i2s.h | 453 + .../TARGET_STM32F0/stm32f0xx_hal_irda.c | 1363 ++ .../TARGET_STM32F0/stm32f0xx_hal_irda.h | 631 + .../TARGET_STM32F0/stm32f0xx_hal_irda_ex.h | 415 + .../TARGET_STM32F0/stm32f0xx_hal_iwdg.c | 415 + .../TARGET_STM32F0/stm32f0xx_hal_iwdg.h | 311 + .../TARGET_STM32F0/stm32f0xx_hal_pcd.c | 1360 ++ .../TARGET_STM32F0/stm32f0xx_hal_pcd.h | 783 + .../TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c | 153 + .../TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h | 103 + .../TARGET_STM32F0/stm32f0xx_hal_pwr.c | 470 + .../TARGET_STM32F0/stm32f0xx_hal_pwr.h | 207 + .../TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c | 292 + .../TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h | 425 + .../TARGET_STM32F0/stm32f0xx_hal_rcc.c | 628 + .../TARGET_STM32F0/stm32f0xx_hal_rcc.h | 1255 ++ .../TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c | 1407 ++ .../TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h | 1680 ++ .../TARGET_STM32F0/stm32f0xx_hal_rtc.c | 1385 ++ .../TARGET_STM32F0/stm32f0xx_hal_rtc.h | 785 + .../TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c | 1577 ++ .../TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h | 708 + .../TARGET_STM32F0/stm32f0xx_hal_smartcard.c | 1431 ++ .../TARGET_STM32F0/stm32f0xx_hal_smartcard.h | 818 + .../stm32f0xx_hal_smartcard_ex.c | 197 + .../stm32f0xx_hal_smartcard_ex.h | 330 + .../TARGET_STM32F0/stm32f0xx_hal_smbus.c | 1939 +++ .../TARGET_STM32F0/stm32f0xx_hal_smbus.h | 617 + .../TARGET_STM32F0/stm32f0xx_hal_spi.c | 2722 +++ .../TARGET_STM32F0/stm32f0xx_hal_spi.h | 677 + .../TARGET_STM32F0/stm32f0xx_hal_tim.c | 5305 ++++++ .../TARGET_STM32F0/stm32f0xx_hal_tim.h | 1645 ++ .../TARGET_STM32F0/stm32f0xx_hal_tim_ex.c | 1835 ++ .../TARGET_STM32F0/stm32f0xx_hal_tim_ex.h | 293 + .../TARGET_STM32F0/stm32f0xx_hal_tsc.c | 791 + .../TARGET_STM32F0/stm32f0xx_hal_tsc.h | 724 + .../TARGET_STM32F0/stm32f0xx_hal_uart.c | 1811 ++ .../TARGET_STM32F0/stm32f0xx_hal_uart.h | 934 + .../TARGET_STM32F0/stm32f0xx_hal_uart_ex.c | 708 + .../TARGET_STM32F0/stm32f0xx_hal_uart_ex.h | 770 + .../TARGET_STM32F0/stm32f0xx_hal_usart.c | 1831 ++ .../TARGET_STM32F0/stm32f0xx_hal_usart.h | 595 + .../TARGET_STM32F0/stm32f0xx_hal_usart_ex.h | 503 + .../TARGET_STM32F0/stm32f0xx_hal_wwdg.c | 449 + .../TARGET_STM32F0/stm32f0xx_hal_wwdg.h | 334 + .../Release_Notes_stm32f1xx_hal.html | 965 ++ .../TOOLCHAIN_GCC_ARM/STM32F100.ld | 156 + .../TOOLCHAIN_GCC_ARM/startup_stm32f100xb.S | 423 + .../TARGET_DISCO_F100RB/cmsis.h | 38 + .../TARGET_DISCO_F100RB/cmsis_nvic.c | 55 + .../TARGET_DISCO_F100RB/cmsis_nvic.h | 54 + .../TARGET_DISCO_F100RB/hal_tick.c | 145 + .../TARGET_DISCO_F100RB/hal_tick.h | 60 + .../TARGET_DISCO_F100RB/stm32f100xb.h | 4073 +++++ .../TARGET_DISCO_F100RB/stm32f1xx.h | 238 + .../TARGET_DISCO_F100RB/system_stm32f1xx.c | 603 + .../TARGET_DISCO_F100RB/system_stm32f1xx.h | 116 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f103xb.S | 300 + .../TOOLCHAIN_ARM_MICRO/stm32f103xb.sct | 44 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f103xb.S | 273 + .../TOOLCHAIN_ARM_STD/stm32f103xb.sct | 44 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F103XB.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f103xb.S | 386 + .../TOOLCHAIN_IAR/startup_stm32f103xb.S | 410 + .../TOOLCHAIN_IAR/stm32f103xb.icf | 33 + .../TARGET_NUCLEO_F103RB/cmsis.h | 38 + .../TARGET_NUCLEO_F103RB/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F103RB/cmsis_nvic.h | 54 + .../TARGET_NUCLEO_F103RB/hal_tick.c | 145 + .../TARGET_NUCLEO_F103RB/hal_tick.h | 60 + .../TARGET_NUCLEO_F103RB/stm32f103xb.h | 5906 +++++++ .../TARGET_NUCLEO_F103RB/stm32f1xx.h | 238 + .../TARGET_NUCLEO_F103RB/system_stm32f1xx.c | 605 + .../TARGET_NUCLEO_F103RB/system_stm32f1xx.h | 116 + .../TARGET_STM32F1/stm32_hal_legacy.h | 2165 +++ .../TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.c | 526 + .../TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.h | 328 + .../TARGET_STM32F1/stm32f1xx_hal_adc.c | 1924 +++ .../TARGET_STM32F1/stm32f1xx_hal_adc.h | 946 + .../TARGET_STM32F1/stm32f1xx_hal_adc_ex.c | 1300 ++ .../TARGET_STM32F1/stm32f1xx_hal_adc_ex.h | 703 + .../TARGET_STM32F1/stm32f1xx_hal_can.c | 1416 ++ .../TARGET_STM32F1/stm32f1xx_hal_can.h | 825 + .../TARGET_STM32F1/stm32f1xx_hal_can_ex.h | 147 + .../TARGET_STM32F1/stm32f1xx_hal_cec.c | 1034 ++ .../TARGET_STM32F1/stm32f1xx_hal_cec.h | 411 + .../TARGET_STM32F1/stm32f1xx_hal_conf.h | 367 + .../TARGET_STM32F1/stm32f1xx_hal_cortex.c | 448 + .../TARGET_STM32F1/stm32f1xx_hal_cortex.h | 222 + .../TARGET_STM32F1/stm32f1xx_hal_crc.c | 341 + .../TARGET_STM32F1/stm32f1xx_hal_crc.h | 195 + .../TARGET_STM32F1/stm32f1xx_hal_dac.c | 929 + .../TARGET_STM32F1/stm32f1xx_hal_dac.h | 324 + .../TARGET_STM32F1/stm32f1xx_hal_dac_ex.c | 659 + .../TARGET_STM32F1/stm32f1xx_hal_dac_ex.h | 398 + .../TARGET_STM32F1/stm32f1xx_hal_def.h | 216 + .../TARGET_STM32F1/stm32f1xx_hal_dma.c | 709 + .../TARGET_STM32F1/stm32f1xx_hal_dma.h | 458 + .../TARGET_STM32F1/stm32f1xx_hal_dma_ex.h | 257 + .../TARGET_STM32F1/stm32f1xx_hal_eth.c | 2000 +++ .../TARGET_STM32F1/stm32f1xx_hal_eth.h | 2135 +++ .../TARGET_STM32F1/stm32f1xx_hal_flash.c | 661 + .../TARGET_STM32F1/stm32f1xx_hal_flash.h | 261 + .../TARGET_STM32F1/stm32f1xx_hal_flash_ex.c | 1650 ++ .../TARGET_STM32F1/stm32f1xx_hal_flash_ex.h | 889 + .../TARGET_STM32F1/stm32f1xx_hal_gpio.c | 596 + .../TARGET_STM32F1/stm32f1xx_hal_gpio.h | 324 + .../TARGET_STM32F1/stm32f1xx_hal_gpio_ex.c | 145 + .../TARGET_STM32F1/stm32f1xx_hal_gpio_ex.h | 887 + .../TARGET_STM32F1/stm32f1xx_hal_hcd.c | 1173 ++ .../TARGET_STM32F1/stm32f1xx_hal_hcd.h | 254 + .../TARGET_STM32F1/stm32f1xx_hal_i2c.c | 3829 ++++ .../TARGET_STM32F1/stm32f1xx_hal_i2c.h | 582 + .../TARGET_STM32F1/stm32f1xx_hal_i2s.c | 1435 ++ .../TARGET_STM32F1/stm32f1xx_hal_i2s.h | 475 + .../TARGET_STM32F1/stm32f1xx_hal_irda.c | 1548 ++ .../TARGET_STM32F1/stm32f1xx_hal_irda.h | 555 + .../TARGET_STM32F1/stm32f1xx_hal_iwdg.c | 358 + .../TARGET_STM32F1/stm32f1xx_hal_iwdg.h | 299 + .../TARGET_STM32F1/stm32f1xx_hal_nand.c | 1173 ++ .../TARGET_STM32F1/stm32f1xx_hal_nand.h | 304 + .../TARGET_STM32F1/stm32f1xx_hal_nor.c | 1050 ++ .../TARGET_STM32F1/stm32f1xx_hal_nor.h | 306 + .../TARGET_STM32F1/stm32f1xx_hal_pccard.c | 742 + .../TARGET_STM32F1/stm32f1xx_hal_pccard.h | 249 + .../TARGET_STM32F1/stm32f1xx_hal_pcd.c | 1410 ++ .../TARGET_STM32F1/stm32f1xx_hal_pcd.h | 825 + .../TARGET_STM32F1/stm32f1xx_hal_pcd_ex.c | 249 + .../TARGET_STM32F1/stm32f1xx_hal_pcd_ex.h | 116 + .../TARGET_STM32F1/stm32f1xx_hal_pwr.c | 636 + .../TARGET_STM32F1/stm32f1xx_hal_pwr.h | 406 + .../TARGET_STM32F1/stm32f1xx_hal_rcc.c | 1085 ++ .../TARGET_STM32F1/stm32f1xx_hal_rcc.h | 1263 ++ .../TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c | 1946 +++ .../TARGET_STM32F1/stm32f1xx_hal_rcc_ex.h | 1895 ++ .../TARGET_STM32F1/stm32f1xx_hal_rtc.c | 1708 ++ .../TARGET_STM32F1/stm32f1xx_hal_rtc.h | 570 + .../TARGET_STM32F1/stm32f1xx_hal_rtc_ex.c | 576 + .../TARGET_STM32F1/stm32f1xx_hal_rtc_ex.h | 430 + .../TARGET_STM32F1/stm32f1xx_hal_sd.c | 3442 ++++ .../TARGET_STM32F1/stm32f1xx_hal_sd.h | 709 + .../TARGET_STM32F1/stm32f1xx_hal_smartcard.c | 1305 ++ .../TARGET_STM32F1/stm32f1xx_hal_smartcard.h | 668 + .../TARGET_STM32F1/stm32f1xx_hal_spi.c | 2398 +++ .../TARGET_STM32F1/stm32f1xx_hal_spi.h | 674 + .../TARGET_STM32F1/stm32f1xx_hal_spi_ex.c | 217 + .../TARGET_STM32F1/stm32f1xx_hal_sram.c | 684 + .../TARGET_STM32F1/stm32f1xx_hal_sram.h | 201 + .../TARGET_STM32F1/stm32f1xx_hal_tim.c | 5329 ++++++ .../TARGET_STM32F1/stm32f1xx_hal_tim.h | 1771 ++ .../TARGET_STM32F1/stm32f1xx_hal_tim_ex.c | 1848 ++ .../TARGET_STM32F1/stm32f1xx_hal_tim_ex.h | 310 + .../TARGET_STM32F1/stm32f1xx_hal_uart.c | 1905 ++ .../TARGET_STM32F1/stm32f1xx_hal_uart.h | 748 + .../TARGET_STM32F1/stm32f1xx_hal_usart.c | 1874 ++ .../TARGET_STM32F1/stm32f1xx_hal_usart.h | 617 + .../TARGET_STM32F1/stm32f1xx_hal_wwdg.c | 458 + .../TARGET_STM32F1/stm32f1xx_hal_wwdg.h | 332 + .../TARGET_STM32F1/stm32f1xx_ll_fsmc.c | 964 ++ .../TARGET_STM32F1/stm32f1xx_ll_fsmc.h | 1080 ++ .../TARGET_STM32F1/stm32f1xx_ll_sdmmc.c | 496 + .../TARGET_STM32F1/stm32f1xx_ll_sdmmc.h | 876 + .../TARGET_STM32F1/stm32f1xx_ll_usb.c | 2210 +++ .../TARGET_STM32F1/stm32f1xx_ll_usb.h | 616 + .../Release_Notes_stm32f3xx_hal.html | 983 ++ .../TOOLCHAIN_GCC_ARM/STM32F303XC.ld | 155 + .../TOOLCHAIN_GCC_ARM/startup_stm32f303xc.S | 478 + .../TARGET_DISCO_F303VC/cmsis.h | 38 + .../TARGET_DISCO_F303VC/cmsis_nvic.c | 55 + .../TARGET_DISCO_F303VC/cmsis_nvic.h | 55 + .../TARGET_DISCO_F303VC/hal_tick.c | 120 + .../TARGET_DISCO_F303VC/hal_tick.h | 60 + .../TARGET_DISCO_F303VC/stm32f303xc.h | 6991 ++++++++ .../TARGET_DISCO_F303VC/stm32f3xx.h | 229 + .../TARGET_DISCO_F303VC/system_stm32f3xx.c | 459 + .../TARGET_DISCO_F303VC/system_stm32f3xx.h | 124 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.S | 355 + .../TOOLCHAIN_ARM_MICRO/stm32f334x8.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f334x8.S | 328 + .../TOOLCHAIN_ARM_STD/stm32f334x8.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F334X8.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S | 430 + .../TOOLCHAIN_IAR/startup_stm32f334x8.S | 485 + .../TOOLCHAIN_IAR/stm32f334x8.icf | 34 + .../TARGET_DISCO_F334C8/cmsis.h | 38 + .../TARGET_DISCO_F334C8/cmsis_nvic.c | 55 + .../TARGET_DISCO_F334C8/cmsis_nvic.h | 55 + .../TARGET_DISCO_F334C8/hal_tick.c | 120 + .../TARGET_DISCO_F334C8/hal_tick.h | 60 + .../TARGET_DISCO_F334C8/stm32f334x8.h | 7604 ++++++++ .../TARGET_DISCO_F334C8/stm32f3xx.h | 238 + .../TARGET_DISCO_F334C8/system_stm32f3xx.c | 457 + .../TARGET_DISCO_F334C8/system_stm32f3xx.h | 124 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.S | 343 + .../TOOLCHAIN_ARM_MICRO/stm32f302x8.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f302x8.S | 316 + .../TOOLCHAIN_ARM_STD/stm32f302x8.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F302X8.ld | 155 + .../TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S | 430 + .../TOOLCHAIN_IAR/startup_stm32f302x8.S | 485 + .../TOOLCHAIN_IAR/stm32f302x8.icf | 31 + .../TARGET_NUCLEO_F302R8/cmsis.h | 38 + .../TARGET_NUCLEO_F302R8/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F302R8/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F302R8/hal_tick.c | 120 + .../TARGET_NUCLEO_F302R8/hal_tick.h | 60 + .../TARGET_NUCLEO_F302R8/stm32f302x8.h | 6367 +++++++ .../TARGET_NUCLEO_F302R8/stm32f3xx.h | 238 + .../TARGET_NUCLEO_F302R8/system_stm32f3xx.c | 457 + .../TARGET_NUCLEO_F302R8/system_stm32f3xx.h | 124 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S | 407 + .../TOOLCHAIN_ARM_MICRO/stm32f303xe.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f303xe.S | 380 + .../TOOLCHAIN_ARM_STD/stm32f303xe.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F303XE.ld | 155 + .../TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S | 505 + .../TOOLCHAIN_IAR/startup_stm32f303xe.S | 610 + .../TOOLCHAIN_IAR/stm32f303xe.icf | 35 + .../TARGET_NUCLEO_F303RE/cmsis.h | 38 + .../TARGET_NUCLEO_F303RE/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F303RE/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F303RE/hal_tick.c | 120 + .../TARGET_NUCLEO_F303RE/hal_tick.h | 60 + .../TARGET_NUCLEO_F303RE/stm32f303xe.h | 8212 +++++++++ .../TARGET_NUCLEO_F303RE/stm32f3xx.h | 238 + .../TARGET_NUCLEO_F303RE/system_stm32f3xx.c | 458 + .../TARGET_NUCLEO_F303RE/system_stm32f3xx.h | 124 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.S | 355 + .../TOOLCHAIN_ARM_MICRO/stm32f334r8.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f334x8.S | 328 + .../TOOLCHAIN_ARM_STD/stm32f334r8.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F334x8.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S | 430 + .../TOOLCHAIN_IAR/startup_stm32f334x8.S | 485 + .../TOOLCHAIN_IAR/stm32f334x8.icf | 34 + .../TARGET_NUCLEO_F334R8/cmsis.h | 38 + .../TARGET_NUCLEO_F334R8/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F334R8/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F334R8/hal_tick.c | 120 + .../TARGET_NUCLEO_F334R8/hal_tick.h | 60 + .../TARGET_NUCLEO_F334R8/stm32f334x8.h | 7604 ++++++++ .../TARGET_NUCLEO_F334R8/stm32f3xx.h | 238 + .../TARGET_NUCLEO_F334R8/system_stm32f3xx.c | 457 + .../TARGET_NUCLEO_F334R8/system_stm32f3xx.h | 124 + .../TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c | 452 + .../TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h | 901 + .../TARGET_STM32F3/stm32f3xx_hal_adc.c | 725 + .../TARGET_STM32F3/stm32f3xx_hal_adc.h | 217 + .../TARGET_STM32F3/stm32f3xx_hal_adc_ex.c | 6281 +++++++ .../TARGET_STM32F3/stm32f3xx_hal_adc_ex.h | 3662 ++++ .../TARGET_STM32F3/stm32f3xx_hal_can.c | 1390 ++ .../TARGET_STM32F3/stm32f3xx_hal_can.h | 822 + .../TARGET_STM32F3/stm32f3xx_hal_cec.c | 1105 ++ .../TARGET_STM32F3/stm32f3xx_hal_cec.h | 593 + .../TARGET_STM32F3/stm32f3xx_hal_comp.c | 709 + .../TARGET_STM32F3/stm32f3xx_hal_comp.h | 275 + .../TARGET_STM32F3/stm32f3xx_hal_comp_ex.h | 1493 ++ .../TARGET_STM32F3/stm32f3xx_hal_conf.h | 331 + .../TARGET_STM32F3/stm32f3xx_hal_cortex.c | 442 + .../TARGET_STM32F3/stm32f3xx_hal_cortex.h | 190 + .../TARGET_STM32F3/stm32f3xx_hal_crc.c | 502 + .../TARGET_STM32F3/stm32f3xx_hal_crc.h | 347 + .../TARGET_STM32F3/stm32f3xx_hal_crc_ex.c | 259 + .../TARGET_STM32F3/stm32f3xx_hal_crc_ex.h | 165 + .../TARGET_STM32F3/stm32f3xx_hal_dac.c | 713 + .../TARGET_STM32F3/stm32f3xx_hal_dac.h | 397 + .../TARGET_STM32F3/stm32f3xx_hal_dac_ex.c | 1067 ++ .../TARGET_STM32F3/stm32f3xx_hal_dac_ex.h | 320 + .../TARGET_STM32F3/stm32f3xx_hal_def.h | 163 + .../TARGET_STM32F3/stm32f3xx_hal_dma.c | 699 + .../TARGET_STM32F3/stm32f3xx_hal_dma.h | 460 + .../TARGET_STM32F3/stm32f3xx_hal_dma_ex.h | 259 + .../TARGET_STM32F3/stm32f3xx_hal_flash.c | 688 + .../TARGET_STM32F3/stm32f3xx_hal_flash.h | 532 + .../TARGET_STM32F3/stm32f3xx_hal_flash_ex.c | 852 + .../TARGET_STM32F3/stm32f3xx_hal_flash_ex.h | 283 + .../TARGET_STM32F3/stm32f3xx_hal_gpio.c | 542 + .../TARGET_STM32F3/stm32f3xx_hal_gpio.h | 307 + .../TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h | 1498 ++ .../TARGET_STM32F3/stm32f3xx_hal_hrtim.c | 7939 +++++++++ .../TARGET_STM32F3/stm32f3xx_hal_hrtim.h | 3589 ++++ .../TARGET_STM32F3/stm32f3xx_hal_i2c.c | 4163 +++++ .../TARGET_STM32F3/stm32f3xx_hal_i2c.h | 591 + .../TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c | 291 + .../TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h | 128 + .../TARGET_STM32F3/stm32f3xx_hal_i2s.c | 1199 ++ .../TARGET_STM32F3/stm32f3xx_hal_i2s.h | 477 + .../TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c | 1557 ++ .../TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h | 225 + .../TARGET_STM32F3/stm32f3xx_hal_irda.c | 1326 ++ .../TARGET_STM32F3/stm32f3xx_hal_irda.h | 626 + .../TARGET_STM32F3/stm32f3xx_hal_irda_ex.h | 415 + .../TARGET_STM32F3/stm32f3xx_hal_iwdg.c | 414 + .../TARGET_STM32F3/stm32f3xx_hal_iwdg.h | 313 + .../TARGET_STM32F3/stm32f3xx_hal_nand.c | 1069 ++ .../TARGET_STM32F3/stm32f3xx_hal_nand.h | 286 + .../TARGET_STM32F3/stm32f3xx_hal_nor.c | 838 + .../TARGET_STM32F3/stm32f3xx_hal_nor.h | 300 + .../TARGET_STM32F3/stm32f3xx_hal_opamp.c | 889 + .../TARGET_STM32F3/stm32f3xx_hal_opamp.h | 509 + .../TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c | 734 + .../TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h | 107 + .../TARGET_STM32F3/stm32f3xx_hal_pccard.c | 725 + .../TARGET_STM32F3/stm32f3xx_hal_pccard.h | 219 + .../TARGET_STM32F3/stm32f3xx_hal_pcd.c | 1302 ++ .../TARGET_STM32F3/stm32f3xx_hal_pcd.h | 798 + .../TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c | 301 + .../TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h | 154 + .../TARGET_STM32F3/stm32f3xx_hal_pwr.c | 445 + .../TARGET_STM32F3/stm32f3xx_hal_pwr.h | 258 + .../TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c | 289 + .../TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h | 299 + .../TARGET_STM32F3/stm32f3xx_hal_rcc.c | 740 + .../TARGET_STM32F3/stm32f3xx_hal_rcc.h | 1102 ++ .../TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c | 1317 ++ .../TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h | 3488 ++++ .../TARGET_STM32F3/stm32f3xx_hal_rtc.c | 1556 ++ .../TARGET_STM32F3/stm32f3xx_hal_rtc.h | 813 + .../TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c | 1577 ++ .../TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h | 707 + .../TARGET_STM32F3/stm32f3xx_hal_sdadc.c | 2648 +++ .../TARGET_STM32F3/stm32f3xx_hal_sdadc.h | 596 + .../TARGET_STM32F3/stm32f3xx_hal_smartcard.c | 1428 ++ .../TARGET_STM32F3/stm32f3xx_hal_smartcard.h | 817 + .../stm32f3xx_hal_smartcard_ex.c | 196 + .../stm32f3xx_hal_smartcard_ex.h | 233 + .../TARGET_STM32F3/stm32f3xx_hal_smbus.c | 1962 +++ .../TARGET_STM32F3/stm32f3xx_hal_smbus.h | 645 + .../TARGET_STM32F3/stm32f3xx_hal_spi.c | 2494 +++ .../TARGET_STM32F3/stm32f3xx_hal_spi.h | 684 + .../TARGET_STM32F3/stm32f3xx_hal_sram.c | 680 + .../TARGET_STM32F3/stm32f3xx_hal_sram.h | 202 + .../TARGET_STM32F3/stm32f3xx_hal_tim.c | 5213 ++++++ .../TARGET_STM32F3/stm32f3xx_hal_tim.h | 1451 ++ .../TARGET_STM32F3/stm32f3xx_hal_tim_ex.c | 2726 +++ .../TARGET_STM32F3/stm32f3xx_hal_tim_ex.h | 1079 ++ .../TARGET_STM32F3/stm32f3xx_hal_tsc.c | 766 + .../TARGET_STM32F3/stm32f3xx_hal_tsc.h | 633 + .../TARGET_STM32F3/stm32f3xx_hal_uart.c | 2021 +++ .../TARGET_STM32F3/stm32f3xx_hal_uart.h | 1064 ++ .../TARGET_STM32F3/stm32f3xx_hal_uart_ex.c | 405 + .../TARGET_STM32F3/stm32f3xx_hal_uart_ex.h | 458 + .../TARGET_STM32F3/stm32f3xx_hal_usart.c | 1769 ++ .../TARGET_STM32F3/stm32f3xx_hal_usart.h | 588 + .../TARGET_STM32F3/stm32f3xx_hal_usart_ex.h | 326 + .../TARGET_STM32F3/stm32f3xx_hal_wwdg.c | 410 + .../TARGET_STM32F3/stm32f3xx_hal_wwdg.h | 311 + .../TARGET_STM32F3/stm32f3xx_ll_fmc.c | 920 + .../TARGET_STM32F3/stm32f3xx_ll_fmc.h | 956 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.S | 342 + .../TOOLCHAIN_ARM_MICRO/stm32f302x8.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f302x8.S | 315 + .../TOOLCHAIN_ARM_STD/stm32f302x8.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F3XX.ld | 157 + .../TOOLCHAIN_GCC_ARM/startup_STM32F30x.S | 465 + .../cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis.h | 38 + .../TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.c | 55 + .../TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.h | 55 + .../TARGET_STM/TARGET_STM32F3XX/stm32f30x.h | 7705 +++++++++ .../TARGET_STM32F3XX/stm32f30x_adc.c | 2411 +++ .../TARGET_STM32F3XX/stm32f30x_adc.h | 830 + .../TARGET_STM32F3XX/stm32f30x_can.c | 1639 ++ .../TARGET_STM32F3XX/stm32f30x_can.h | 653 + .../TARGET_STM32F3XX/stm32f30x_comp.c | 514 + .../TARGET_STM32F3XX/stm32f30x_comp.h | 436 + .../TARGET_STM32F3XX/stm32f30x_conf.h | 94 + .../TARGET_STM32F3XX/stm32f30x_crc.c | 364 + .../TARGET_STM32F3XX/stm32f30x_crc.h | 131 + .../TARGET_STM32F3XX/stm32f30x_dac.c | 764 + .../TARGET_STM32F3XX/stm32f30x_dac.h | 332 + .../TARGET_STM32F3XX/stm32f30x_dbgmcu.c | 223 + .../TARGET_STM32F3XX/stm32f30x_dbgmcu.h | 118 + .../TARGET_STM32F3XX/stm32f30x_dma.c | 876 + .../TARGET_STM32F3XX/stm32f30x_dma.h | 446 + .../TARGET_STM32F3XX/stm32f30x_exti.c | 359 + .../TARGET_STM32F3XX/stm32f30x_exti.h | 244 + .../TARGET_STM32F3XX/stm32f30x_flash.c | 1180 ++ .../TARGET_STM32F3XX/stm32f30x_flash.h | 339 + .../TARGET_STM32F3XX/stm32f30x_gpio.c | 545 + .../TARGET_STM32F3XX/stm32f30x_gpio.h | 410 + .../TARGET_STM32F3XX/stm32f30x_hrtim.c | 3968 +++++ .../TARGET_STM32F3XX/stm32f30x_hrtim.h | 2723 +++ .../TARGET_STM32F3XX/stm32f30x_i2c.c | 1595 ++ .../TARGET_STM32F3XX/stm32f30x_i2c.h | 487 + .../TARGET_STM32F3XX/stm32f30x_iwdg.c | 298 + .../TARGET_STM32F3XX/stm32f30x_iwdg.h | 163 + .../TARGET_STM32F3XX/stm32f30x_misc.c | 240 + .../TARGET_STM32F3XX/stm32f30x_misc.h | 214 + .../TARGET_STM32F3XX/stm32f30x_opamp.c | 585 + .../TARGET_STM32F3XX/stm32f30x_opamp.h | 287 + .../TARGET_STM32F3XX/stm32f30x_pwr.c | 548 + .../TARGET_STM32F3XX/stm32f30x_pwr.h | 197 + .../TARGET_STM32F3XX/stm32f30x_rcc.c | 1961 +++ .../TARGET_STM32F3XX/stm32f30x_rcc.h | 709 + .../TARGET_STM32F3XX/stm32f30x_rtc.c | 2608 +++ .../TARGET_STM32F3XX/stm32f30x_rtc.h | 862 + .../TARGET_STM32F3XX/stm32f30x_spi.c | 1420 ++ .../TARGET_STM32F3XX/stm32f30x_spi.h | 616 + .../TARGET_STM32F3XX/stm32f30x_syscfg.c | 533 + .../TARGET_STM32F3XX/stm32f30x_syscfg.h | 355 + .../TARGET_STM32F3XX/stm32f30x_tim.c | 4005 +++++ .../TARGET_STM32F3XX/stm32f30x_tim.h | 1344 ++ .../TARGET_STM32F3XX/stm32f30x_usart.c | 2094 +++ .../TARGET_STM32F3XX/stm32f30x_usart.h | 617 + .../TARGET_STM32F3XX/stm32f30x_wwdg.c | 314 + .../TARGET_STM32F3XX/stm32f30x_wwdg.h | 119 + .../TARGET_STM32F3XX/system_stm32f30x.c | 478 + .../TARGET_STM32F3XX/system_stm32f30x.h | 86 + .../Release_Notes_stm32f4xx_hal.html | 1480 ++ .../TOOLCHAIN_GCC_ARM/STM32F401XC.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f401xc.S | 455 + .../TARGET_DISCO_F401VC/cmsis.h | 38 + .../TARGET_DISCO_F401VC/cmsis_nvic.c | 55 + .../TARGET_DISCO_F401VC/cmsis_nvic.h | 55 + .../TARGET_DISCO_F401VC/hal_tick.c | 123 + .../TARGET_DISCO_F401VC/hal_tick.h | 60 + .../TARGET_DISCO_F401VC/stm32f401xc.h | 4777 +++++ .../TARGET_DISCO_F401VC/stm32f4xx.h | 232 + .../TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h | 406 + .../TARGET_DISCO_F401VC/system_stm32f4xx.c | 702 + .../TARGET_DISCO_F401VC/system_stm32f4xx.h | 123 + .../TOOLCHAIN_GCC_ARM/STM32F429ZI.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S | 566 + .../TOOLCHAIN_IAR/startup_stm32f429xx.S | 693 + .../TOOLCHAIN_IAR/stm32f429xx_flash.icf | 37 + .../TARGET_DISCO_F429ZI/cmsis.h | 38 + .../TARGET_DISCO_F429ZI/cmsis_nvic.c | 55 + .../TARGET_DISCO_F429ZI/cmsis_nvic.h | 55 + .../TARGET_DISCO_F429ZI/hal_tick.c | 124 + .../TARGET_DISCO_F429ZI/hal_tick.h | 60 + .../TARGET_DISCO_F429ZI/stm32f429xx.h | 9038 ++++++++++ .../TARGET_DISCO_F429ZI/stm32f4xx.h | 232 + .../TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h | 406 + .../TARGET_DISCO_F429ZI/system_stm32f4xx.c | 631 + .../TARGET_DISCO_F429ZI/system_stm32f4xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S | 373 + .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 47 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f411xe.S | 346 + .../TOOLCHAIN_ARM_STD/stm32f411re.sct | 47 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_STM32F41x.S | 297 + .../TOOLCHAIN_IAR/startup_stm32f411xe.S | 523 + .../TOOLCHAIN_IAR/stm32f411xe.icf | 32 + .../TARGET_MTS_DRAGONFLY_F411RE/cmsis.h | 38 + .../TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c | 55 + .../TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.h | 55 + .../TARGET_MTS_DRAGONFLY_F411RE/hal_tick.c | 122 + .../TARGET_MTS_DRAGONFLY_F411RE/hal_tick.h | 60 + .../TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h | 4803 +++++ .../TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h | 232 + .../stm32f4xx_hal_conf.h | 405 + .../system_stm32f4xx.c | 707 + .../system_stm32f4xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.S | 413 + .../TOOLCHAIN_ARM_MICRO/stm32f405xx.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f405xx.S | 387 + .../TOOLCHAIN_ARM_STD/stm32f405xx.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F405.ld | 151 + .../TOOLCHAIN_GCC_ARM/startup_STM32F40x.S | 316 + .../TOOLCHAIN_IAR/startup_stm32f405xx.S | 623 + .../TOOLCHAIN_IAR/stm32f405xx.icf | 38 + .../TARGET_MTS_MDOT_F405RG/cmsis.h | 38 + .../TARGET_MTS_MDOT_F405RG/cmsis_nvic.c | 55 + .../TARGET_MTS_MDOT_F405RG/cmsis_nvic.h | 55 + .../TARGET_MTS_MDOT_F405RG/hal_tick.c | 120 + .../TARGET_MTS_MDOT_F405RG/hal_tick.h | 60 + .../TARGET_MTS_MDOT_F405RG/stm32f405xx.h | 7458 ++++++++ .../TARGET_MTS_MDOT_F405RG/stm32f4xx.h | 232 + .../stm32f4xx_hal_conf.h | 407 + .../TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c | 572 + .../TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S | 373 + .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 47 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f411xe.S | 346 + .../TOOLCHAIN_ARM_STD/stm32f411re.sct | 47 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F411XE.ld | 155 + .../TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S | 459 + .../TOOLCHAIN_IAR/startup_stm32f411xe.S | 523 + .../TOOLCHAIN_IAR/stm32f411xe.icf | 31 + .../TARGET_MTS_MDOT_F411RE/cmsis.h | 38 + .../TARGET_MTS_MDOT_F411RE/cmsis_nvic.c | 55 + .../TARGET_MTS_MDOT_F411RE/cmsis_nvic.h | 55 + .../TARGET_MTS_MDOT_F411RE/hal_tick.c | 122 + .../TARGET_MTS_MDOT_F411RE/hal_tick.h | 60 + .../TARGET_MTS_MDOT_F411RE/stm32f411xe.h | 4803 +++++ .../TARGET_MTS_MDOT_F411RE/stm32f4xx.h | 232 + .../stm32f4xx_hal_conf.h | 405 + .../TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c | 708 + .../TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.S | 368 + .../TOOLCHAIN_ARM_MICRO/stm32f401xe.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f401xe.S | 342 + .../TOOLCHAIN_ARM_STD/stm32f401xe.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F401XE.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S | 455 + .../TOOLCHAIN_IAR/startup_stm32f401xe.S | 517 + .../TOOLCHAIN_IAR/stm32f401xe.icf | 33 + .../TARGET_NUCLEO_F401RE/cmsis.h | 38 + .../TARGET_NUCLEO_F401RE/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F401RE/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F401RE/hal_tick.c | 123 + .../TARGET_NUCLEO_F401RE/hal_tick.h | 60 + .../TARGET_NUCLEO_F401RE/stm32f401xe.h | 4777 +++++ .../TARGET_NUCLEO_F401RE/stm32f4xx.h | 232 + .../TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h | 405 + .../TARGET_NUCLEO_F401RE/system_stm32f4xx.c | 702 + .../TARGET_NUCLEO_F401RE/system_stm32f4xx.h | 124 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S | 373 + .../TOOLCHAIN_ARM_MICRO/stm32f411re.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f411xe.S | 346 + .../TOOLCHAIN_ARM_STD/stm32f411re.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F411XE.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S | 459 + .../TOOLCHAIN_IAR/startup_stm32f411xe.S | 523 + .../TOOLCHAIN_IAR/stm32f411xe.icf | 31 + .../TARGET_NUCLEO_F411RE/cmsis.h | 38 + .../TARGET_NUCLEO_F411RE/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F411RE/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F411RE/hal_tick.c | 122 + .../TARGET_NUCLEO_F411RE/hal_tick.h | 60 + .../TARGET_NUCLEO_F411RE/stm32f411xe.h | 4803 +++++ .../TARGET_NUCLEO_F411RE/stm32f4xx.h | 232 + .../TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h | 405 + .../TARGET_NUCLEO_F411RE/system_stm32f4xx.c | 706 + .../TARGET_NUCLEO_F411RE/system_stm32f4xx.h | 123 + .../TOOLCHAIN_GCC_ARM/STM32F446XE.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f446xx.S | 559 + .../TARGET_NUCLEO_F446RE/cmsis.h | 38 + .../TARGET_NUCLEO_F446RE/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_F446RE/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_F446RE/hal_tick.c | 122 + .../TARGET_NUCLEO_F446RE/hal_tick.h | 60 + .../TARGET_NUCLEO_F446RE/stm32f446xx.h | 8217 +++++++++ .../TARGET_NUCLEO_F446RE/stm32f4xx.h | 232 + .../TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h | 405 + .../TARGET_NUCLEO_F446RE/system_stm32f4xx.c | 712 + .../TARGET_NUCLEO_F446RE/system_stm32f4xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/STM32F407.sct | 17 + .../TOOLCHAIN_ARM_MICRO/startup_STM32F40x.S | 395 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/STM32F407.sct | 17 + .../TOOLCHAIN_ARM_STD/startup_STM32F40x.S | 369 + .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/STM32F407XG.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f407xx.S | 528 + .../TARGET_STM32F4/TARGET_STM32F407VG/cmsis.h | 38 + .../TARGET_STM32F407VG/cmsis_nvic.c | 55 + .../TARGET_STM32F407VG/cmsis_nvic.h | 61 + .../TARGET_STM32F407VG/hal_tick.c | 124 + .../TARGET_STM32F407VG/hal_tick.h | 60 + .../TARGET_STM32F407VG/stm32f407xx.h | 8062 +++++++++ .../TARGET_STM32F407VG/stm32f4xx.h | 232 + .../TARGET_STM32F407VG/stm32f4xx_hal_conf.h | 407 + .../TARGET_STM32F407VG/system_stm32f4xx.c | 704 + .../TARGET_STM32F407VG/system_stm32f4xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S | 445 + .../TOOLCHAIN_ARM_MICRO/stm32f439xx.sct | 48 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f439xx.S | 467 + .../TOOLCHAIN_ARM_STD/stm32f439xx.sct | 48 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F439ZI.ld | 154 + .../TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S | 570 + .../TOOLCHAIN_IAR/startup_stm32f439xx.S | 698 + .../TOOLCHAIN_IAR/stm32f439xx_flash.icf | 35 + .../TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h | 38 + .../TARGET_UBLOX_C029/cmsis_nvic.c | 55 + .../TARGET_UBLOX_C029/cmsis_nvic.h | 55 + .../TARGET_UBLOX_C029/hal_tick.c | 120 + .../TARGET_UBLOX_C029/hal_tick.h | 60 + .../TARGET_UBLOX_C029/stm32f439xx.h | 9218 ++++++++++ .../TARGET_UBLOX_C029/stm32f4xx.h | 232 + .../TARGET_UBLOX_C029/stm32f4xx_hal_conf.h | 406 + .../TARGET_UBLOX_C029/system_stm32f4xx.c | 709 + .../TARGET_UBLOX_C029/system_stm32f4xx.h | 123 + .../TARGET_STM32F4/stm32_hal_legacy.h | 2307 +++ .../TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c | 531 + .../TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h | 233 + .../TARGET_STM32F4/stm32f4xx_hal_adc.c | 1412 ++ .../TARGET_STM32F4/stm32f4xx_hal_adc.h | 762 + .../TARGET_STM32F4/stm32f4xx_hal_adc_ex.c | 854 + .../TARGET_STM32F4/stm32f4xx_hal_adc_ex.h | 350 + .../TARGET_STM32F4/stm32f4xx_hal_can.c | 1438 ++ .../TARGET_STM32F4/stm32f4xx_hal_can.h | 775 + .../TARGET_STM32F4/stm32f4xx_hal_cec.c | 1112 ++ .../TARGET_STM32F4/stm32f4xx_hal_cec.h | 681 + .../TARGET_STM32F4/stm32f4xx_hal_cortex.c | 436 + .../TARGET_STM32F4/stm32f4xx_hal_cortex.h | 200 + .../TARGET_STM32F4/stm32f4xx_hal_crc.c | 342 + .../TARGET_STM32F4/stm32f4xx_hal_crc.h | 249 + .../TARGET_STM32F4/stm32f4xx_hal_cryp.c | 3813 ++++ .../TARGET_STM32F4/stm32f4xx_hal_cryp.h | 536 + .../TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c | 3043 ++++ .../TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h | 221 + .../TARGET_STM32F4/stm32f4xx_hal_dac.c | 928 + .../TARGET_STM32F4/stm32f4xx_hal_dac.h | 412 + .../TARGET_STM32F4/stm32f4xx_hal_dac_ex.c | 382 + .../TARGET_STM32F4/stm32f4xx_hal_dac_ex.h | 199 + .../TARGET_STM32F4/stm32f4xx_hal_dcmi.c | 830 + .../TARGET_STM32F4/stm32f4xx_hal_dcmi.h | 515 + .../TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c | 212 + .../TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h | 221 + .../TARGET_STM32F4/stm32f4xx_hal_def.h | 217 + .../TARGET_STM32F4/stm32f4xx_hal_dma.c | 928 + .../TARGET_STM32F4/stm32f4xx_hal_dma.h | 767 + .../TARGET_STM32F4/stm32f4xx_hal_dma2d.c | 1266 ++ .../TARGET_STM32F4/stm32f4xx_hal_dma2d.h | 554 + .../TARGET_STM32F4/stm32f4xx_hal_dma_ex.c | 307 + .../TARGET_STM32F4/stm32f4xx_hal_dma_ex.h | 123 + .../TARGET_STM32F4/stm32f4xx_hal_eth.c | 2017 +++ .../TARGET_STM32F4/stm32f4xx_hal_eth.h | 2223 +++ .../TARGET_STM32F4/stm32f4xx_hal_flash.c | 761 + .../TARGET_STM32F4/stm32f4xx_hal_flash.h | 435 + .../TARGET_STM32F4/stm32f4xx_hal_flash_ex.c | 1308 ++ .../TARGET_STM32F4/stm32f4xx_hal_flash_ex.h | 866 + .../stm32f4xx_hal_flash_ramfunc.c | 194 + .../stm32f4xx_hal_flash_ramfunc.h | 97 + .../TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c | 4098 +++++ .../TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h | 577 + .../TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c | 326 + .../TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h | 151 + .../TARGET_STM32F4/stm32f4xx_hal_gpio.c | 545 + .../TARGET_STM32F4/stm32f4xx_hal_gpio.h | 327 + .../TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h | 1100 ++ .../TARGET_STM32F4/stm32f4xx_hal_hash.c | 1843 ++ .../TARGET_STM32F4/stm32f4xx_hal_hash.h | 448 + .../TARGET_STM32F4/stm32f4xx_hal_hash_ex.c | 1625 ++ .../TARGET_STM32F4/stm32f4xx_hal_hash_ex.h | 200 + .../TARGET_STM32F4/stm32f4xx_hal_hcd.c | 1198 ++ .../TARGET_STM32F4/stm32f4xx_hal_hcd.h | 282 + .../TARGET_STM32F4/stm32f4xx_hal_i2c.c | 3685 ++++ .../TARGET_STM32F4/stm32f4xx_hal_i2c.h | 535 + .../TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c | 204 + .../TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h | 136 + .../TARGET_STM32F4/stm32f4xx_hal_i2s.c | 1405 ++ .../TARGET_STM32F4/stm32f4xx_hal_i2s.h | 511 + .../TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c | 1479 ++ .../TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h | 148 + .../TARGET_STM32F4/stm32f4xx_hal_irda.c | 1504 ++ .../TARGET_STM32F4/stm32f4xx_hal_irda.h | 538 + .../TARGET_STM32F4/stm32f4xx_hal_iwdg.c | 361 + .../TARGET_STM32F4/stm32f4xx_hal_iwdg.h | 288 + .../TARGET_STM32F4/stm32f4xx_hal_ltdc.c | 1191 ++ .../TARGET_STM32F4/stm32f4xx_hal_ltdc.h | 631 + .../stm32f4xx_hal_msp_template.c | 119 + .../TARGET_STM32F4/stm32f4xx_hal_nand.c | 1125 ++ .../TARGET_STM32F4/stm32f4xx_hal_nand.h | 316 + .../TARGET_STM32F4/stm32f4xx_hal_nor.c | 1007 ++ .../TARGET_STM32F4/stm32f4xx_hal_nor.h | 301 + .../TARGET_STM32F4/stm32f4xx_hal_pccard.c | 742 + .../TARGET_STM32F4/stm32f4xx_hal_pccard.h | 267 + .../TARGET_STM32F4/stm32f4xx_hal_pcd.c | 1208 ++ .../TARGET_STM32F4/stm32f4xx_hal_pcd.h | 322 + .../TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c | 199 + .../TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h | 105 + .../TARGET_STM32F4/stm32f4xx_hal_pwr.c | 574 + .../TARGET_STM32F4/stm32f4xx_hal_pwr.h | 484 + .../TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c | 624 + .../TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h | 291 + .../TARGET_STM32F4/stm32f4xx_hal_qspi.c | 1942 +++ .../TARGET_STM32F4/stm32f4xx_hal_qspi.h | 788 + .../TARGET_STM32F4/stm32f4xx_hal_rcc.c | 1234 ++ .../TARGET_STM32F4/stm32f4xx_hal_rcc.h | 1537 ++ .../TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c | 1682 ++ .../TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h | 2707 +++ .../TARGET_STM32F4/stm32f4xx_hal_rng.c | 515 + .../TARGET_STM32F4/stm32f4xx_hal_rng.h | 364 + .../TARGET_STM32F4/stm32f4xx_hal_rtc.c | 1538 ++ .../TARGET_STM32F4/stm32f4xx_hal_rtc.h | 823 + .../TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c | 1709 ++ .../TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h | 1015 ++ .../TARGET_STM32F4/stm32f4xx_hal_sai.c | 1908 ++ .../TARGET_STM32F4/stm32f4xx_hal_sai.h | 908 + .../TARGET_STM32F4/stm32f4xx_hal_sai_ex.c | 269 + .../TARGET_STM32F4/stm32f4xx_hal_sai_ex.h | 101 + .../TARGET_STM32F4/stm32f4xx_hal_sd.c | 3488 ++++ .../TARGET_STM32F4/stm32f4xx_hal_sd.h | 789 + .../TARGET_STM32F4/stm32f4xx_hal_sdram.c | 842 + .../TARGET_STM32F4/stm32f4xx_hal_sdram.h | 196 + .../TARGET_STM32F4/stm32f4xx_hal_smartcard.c | 1303 ++ .../TARGET_STM32F4/stm32f4xx_hal_smartcard.h | 620 + .../TARGET_STM32F4/stm32f4xx_hal_spdifrx.c | 1210 ++ .../TARGET_STM32F4/stm32f4xx_hal_spdifrx.h | 559 + .../TARGET_STM32F4/stm32f4xx_hal_spi.c | 2300 +++ .../TARGET_STM32F4/stm32f4xx_hal_spi.h | 575 + .../TARGET_STM32F4/stm32f4xx_hal_sram.c | 682 + .../TARGET_STM32F4/stm32f4xx_hal_sram.h | 202 + .../TARGET_STM32F4/stm32f4xx_hal_tim.c | 5335 ++++++ .../TARGET_STM32F4/stm32f4xx_hal_tim.h | 1608 ++ .../TARGET_STM32F4/stm32f4xx_hal_tim_ex.c | 1864 ++ .../TARGET_STM32F4/stm32f4xx_hal_tim_ex.h | 325 + .../TARGET_STM32F4/stm32f4xx_hal_uart.c | 1932 +++ .../TARGET_STM32F4/stm32f4xx_hal_uart.h | 722 + .../TARGET_STM32F4/stm32f4xx_hal_usart.c | 1857 ++ .../TARGET_STM32F4/stm32f4xx_hal_usart.h | 588 + .../TARGET_STM32F4/stm32f4xx_hal_wwdg.c | 454 + .../TARGET_STM32F4/stm32f4xx_hal_wwdg.h | 349 + .../TARGET_STM32F4/stm32f4xx_ll_fmc.c | 1735 ++ .../TARGET_STM32F4/stm32f4xx_ll_fmc.h | 1421 ++ .../TARGET_STM32F4/stm32f4xx_ll_fsmc.c | 955 + .../TARGET_STM32F4/stm32f4xx_ll_fsmc.h | 978 ++ .../TARGET_STM32F4/stm32f4xx_ll_sdmmc.c | 505 + .../TARGET_STM32F4/stm32f4xx_ll_sdmmc.h | 908 + .../TARGET_STM32F4/stm32f4xx_ll_usb.c | 1705 ++ .../TARGET_STM32F4/stm32f4xx_ll_usb.h | 463 + .../TOOLCHAIN_ARM_STD/STM32F407.sct | 17 + .../TOOLCHAIN_ARM_STD/startup_STM32F40x.S | 369 + .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/STM32F407.ld | 151 + .../TOOLCHAIN_GCC_ARM/startup_STM32F40x.S | 320 + .../TOOLCHAIN_IAR/STM32F407.icf | 38 + .../TOOLCHAIN_IAR/startup_STM32F40x.S | 636 + .../cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis.h | 14 + .../TARGET_STM/TARGET_STM32F4XX/cmsis_nvic.c | 33 + .../TARGET_STM/TARGET_STM32F4XX/cmsis_nvic.h | 26 + .../TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h | 7155 ++++++++ .../TARGET_STM32F4XX/system_stm32f4xx.c | 573 + .../TARGET_STM32F4XX/system_stm32f4xx.h | 105 + .../Release_Notes_stm32f7xx_hal.html | 740 + .../TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S | 463 + .../TOOLCHAIN_ARM_MICRO/stm32f746ng.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32f746ng.S | 436 + .../TOOLCHAIN_ARM_STD/stm32f746ng.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32F746NG.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S | 596 + .../TOOLCHAIN_IAR/startup_stm32f746xx.S | 732 + .../TOOLCHAIN_IAR/stm32f746ng.icf | 35 + .../TARGET_DISCO_F746NG/cmsis.h | 38 + .../TARGET_DISCO_F746NG/cmsis_nvic.c | 55 + .../TARGET_DISCO_F746NG/cmsis_nvic.h | 54 + .../TARGET_DISCO_F746NG/hal_tick.c | 134 + .../TARGET_DISCO_F746NG/hal_tick.h | 62 + .../TARGET_DISCO_F746NG/stm32f746xx.h | 9435 ++++++++++ .../TARGET_DISCO_F746NG/stm32f7xx.h | 197 + .../TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h | 421 + .../TARGET_DISCO_F746NG/system_stm32f7xx.c | 694 + .../TARGET_DISCO_F746NG/system_stm32f7xx.h | 123 + .../TARGET_STM32F7/stm32_hal_legacy.h | 2494 +++ .../TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c | 492 + .../TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h | 171 + .../TARGET_STM32F7/stm32f7xx_hal_adc.c | 1408 ++ .../TARGET_STM32F7/stm32f7xx_hal_adc.h | 765 + .../TARGET_STM32F7/stm32f7xx_hal_adc_ex.c | 854 + .../TARGET_STM32F7/stm32f7xx_hal_adc_ex.h | 329 + .../TARGET_STM32F7/stm32f7xx_hal_can.c | 1436 ++ .../TARGET_STM32F7/stm32f7xx_hal_can.h | 769 + .../TARGET_STM32F7/stm32f7xx_hal_cec.c | 1109 ++ .../TARGET_STM32F7/stm32f7xx_hal_cec.h | 679 + .../TARGET_STM32F7/stm32f7xx_hal_cortex.c | 483 + .../TARGET_STM32F7/stm32f7xx_hal_cortex.h | 490 + .../TARGET_STM32F7/stm32f7xx_hal_crc.c | 509 + .../TARGET_STM32F7/stm32f7xx_hal_crc.h | 423 + .../TARGET_STM32F7/stm32f7xx_hal_crc_ex.c | 242 + .../TARGET_STM32F7/stm32f7xx_hal_crc_ex.h | 168 + .../TARGET_STM32F7/stm32f7xx_hal_cryp.c | 3808 ++++ .../TARGET_STM32F7/stm32f7xx_hal_cryp.h | 536 + .../TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c | 3040 ++++ .../TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h | 221 + .../TARGET_STM32F7/stm32f7xx_hal_dac.c | 949 + .../TARGET_STM32F7/stm32f7xx_hal_dac.h | 408 + .../TARGET_STM32F7/stm32f7xx_hal_dac_ex.c | 376 + .../TARGET_STM32F7/stm32f7xx_hal_dac_ex.h | 191 + .../TARGET_STM32F7/stm32f7xx_hal_dcmi.c | 827 + .../TARGET_STM32F7/stm32f7xx_hal_dcmi.h | 497 + .../TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c | 201 + .../TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h | 213 + .../TARGET_STM32F7/stm32f7xx_hal_def.h | 213 + .../TARGET_STM32F7/stm32f7xx_hal_dma.c | 921 + .../TARGET_STM32F7/stm32f7xx_hal_dma.h | 772 + .../TARGET_STM32F7/stm32f7xx_hal_dma2d.c | 1263 ++ .../TARGET_STM32F7/stm32f7xx_hal_dma2d.h | 559 + .../TARGET_STM32F7/stm32f7xx_hal_dma_ex.c | 301 + .../TARGET_STM32F7/stm32f7xx_hal_dma_ex.h | 123 + .../TARGET_STM32F7/stm32f7xx_hal_eth.c | 2011 +++ .../TARGET_STM32F7/stm32f7xx_hal_eth.h | 2220 +++ .../TARGET_STM32F7/stm32f7xx_hal_flash.c | 817 + .../TARGET_STM32F7/stm32f7xx_hal_flash.h | 390 + .../TARGET_STM32F7/stm32f7xx_hal_flash_ex.c | 807 + .../TARGET_STM32F7/stm32f7xx_hal_flash_ex.h | 468 + .../TARGET_STM32F7/stm32f7xx_hal_gpio.c | 540 + .../TARGET_STM32F7/stm32f7xx_hal_gpio.h | 327 + .../TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h | 377 + .../TARGET_STM32F7/stm32f7xx_hal_hash.c | 1843 ++ .../TARGET_STM32F7/stm32f7xx_hal_hash.h | 446 + .../TARGET_STM32F7/stm32f7xx_hal_hash_ex.c | 1624 ++ .../TARGET_STM32F7/stm32f7xx_hal_hash_ex.h | 199 + .../TARGET_STM32F7/stm32f7xx_hal_hcd.c | 1199 ++ .../TARGET_STM32F7/stm32f7xx_hal_hcd.h | 277 + .../TARGET_STM32F7/stm32f7xx_hal_i2c.c | 4110 +++++ .../TARGET_STM32F7/stm32f7xx_hal_i2c.h | 598 + .../TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c | 210 + .../TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h | 129 + .../TARGET_STM32F7/stm32f7xx_hal_i2s.c | 1531 ++ .../TARGET_STM32F7/stm32f7xx_hal_i2s.h | 483 + .../TARGET_STM32F7/stm32f7xx_hal_irda.c | 1495 ++ .../TARGET_STM32F7/stm32f7xx_hal_irda.h | 643 + .../TARGET_STM32F7/stm32f7xx_hal_irda_ex.h | 239 + .../TARGET_STM32F7/stm32f7xx_hal_iwdg.c | 423 + .../TARGET_STM32F7/stm32f7xx_hal_iwdg.h | 308 + .../TARGET_STM32F7/stm32f7xx_hal_lptim.c | 1653 ++ .../TARGET_STM32F7/stm32f7xx_hal_lptim.h | 648 + .../TARGET_STM32F7/stm32f7xx_hal_ltdc.c | 1193 ++ .../TARGET_STM32F7/stm32f7xx_hal_ltdc.h | 630 + .../TARGET_STM32F7/stm32f7xx_hal_nand.c | 1014 ++ .../TARGET_STM32F7/stm32f7xx_hal_nand.h | 301 + .../TARGET_STM32F7/stm32f7xx_hal_nor.c | 1014 ++ .../TARGET_STM32F7/stm32f7xx_hal_nor.h | 299 + .../TARGET_STM32F7/stm32f7xx_hal_pcd.c | 1202 ++ .../TARGET_STM32F7/stm32f7xx_hal_pcd.h | 326 + .../TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c | 197 + .../TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h | 101 + .../TARGET_STM32F7/stm32f7xx_hal_pwr.c | 609 + .../TARGET_STM32F7/stm32f7xx_hal_pwr.h | 424 + .../TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c | 564 + .../TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h | 280 + .../TARGET_STM32F7/stm32f7xx_hal_qspi.c | 1935 +++ .../TARGET_STM32F7/stm32f7xx_hal_qspi.h | 786 + .../TARGET_STM32F7/stm32f7xx_hal_rcc.c | 1197 ++ .../TARGET_STM32F7/stm32f7xx_hal_rcc.h | 1304 ++ .../TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c | 860 + .../TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h | 2698 +++ .../TARGET_STM32F7/stm32f7xx_hal_rng.c | 510 + .../TARGET_STM32F7/stm32f7xx_hal_rng.h | 358 + .../TARGET_STM32F7/stm32f7xx_hal_rtc.c | 1545 ++ .../TARGET_STM32F7/stm32f7xx_hal_rtc.h | 806 + .../TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c | 1805 ++ .../TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h | 1022 ++ .../TARGET_STM32F7/stm32f7xx_hal_sai.c | 1900 ++ .../TARGET_STM32F7/stm32f7xx_hal_sai.h | 904 + .../TARGET_STM32F7/stm32f7xx_hal_sai_ex.c | 179 + .../TARGET_STM32F7/stm32f7xx_hal_sai_ex.h | 98 + .../TARGET_STM32F7/stm32f7xx_hal_sd.c | 3381 ++++ .../TARGET_STM32F7/stm32f7xx_hal_sd.h | 774 + .../TARGET_STM32F7/stm32f7xx_hal_sdram.c | 844 + .../TARGET_STM32F7/stm32f7xx_hal_sdram.h | 199 + .../TARGET_STM32F7/stm32f7xx_hal_smartcard.c | 1321 ++ .../TARGET_STM32F7/stm32f7xx_hal_smartcard.h | 831 + .../stm32f7xx_hal_smartcard_ex.c | 184 + .../stm32f7xx_hal_smartcard_ex.h | 175 + .../TARGET_STM32F7/stm32f7xx_hal_spdifrx.c | 1208 ++ .../TARGET_STM32F7/stm32f7xx_hal_spdifrx.h | 556 + .../TARGET_STM32F7/stm32f7xx_hal_spi.c | 2728 +++ .../TARGET_STM32F7/stm32f7xx_hal_spi.h | 696 + .../TARGET_STM32F7/stm32f7xx_hal_sram.c | 678 + .../TARGET_STM32F7/stm32f7xx_hal_sram.h | 195 + .../TARGET_STM32F7/stm32f7xx_hal_tim.c | 5459 ++++++ .../TARGET_STM32F7/stm32f7xx_hal_tim.h | 1546 ++ .../TARGET_STM32F7/stm32f7xx_hal_tim_ex.c | 2481 +++ .../TARGET_STM32F7/stm32f7xx_hal_tim_ex.h | 552 + .../TARGET_STM32F7/stm32f7xx_hal_uart.c | 1993 +++ .../TARGET_STM32F7/stm32f7xx_hal_uart.h | 1165 ++ .../TARGET_STM32F7/stm32f7xx_hal_uart_ex.h | 335 + .../TARGET_STM32F7/stm32f7xx_hal_usart.c | 1798 ++ .../TARGET_STM32F7/stm32f7xx_hal_usart.h | 696 + .../TARGET_STM32F7/stm32f7xx_hal_usart_ex.h | 158 + .../TARGET_STM32F7/stm32f7xx_hal_wwdg.c | 454 + .../TARGET_STM32F7/stm32f7xx_hal_wwdg.h | 337 + .../TARGET_STM32F7/stm32f7xx_ll_fmc.c | 1123 ++ .../TARGET_STM32F7/stm32f7xx_ll_fmc.h | 1337 ++ .../TARGET_STM32F7/stm32f7xx_ll_sdmmc.c | 510 + .../TARGET_STM32F7/stm32f7xx_ll_sdmmc.h | 804 + .../TARGET_STM32F7/stm32f7xx_ll_usb.c | 1690 ++ .../TARGET_STM32F7/stm32f7xx_ll_usb.h | 463 + .../Release_Notes_stm32l0xx_hal.html | 1140 ++ .../TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S | 242 + .../TOOLCHAIN_ARM_MICRO/stm32l053c8.sct | 44 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l053xx.S | 215 + .../TOOLCHAIN_ARM_STD/stm32l053c8.sct | 44 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L053X8.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S | 299 + .../TOOLCHAIN_IAR/startup_stm32l053xx.S | 332 + .../TOOLCHAIN_IAR/stm32l053xx.icf | 30 + .../TARGET_DISCO_L053C8/cmsis.h | 38 + .../TARGET_DISCO_L053C8/cmsis_nvic.c | 55 + .../TARGET_DISCO_L053C8/cmsis_nvic.h | 54 + .../TARGET_DISCO_L053C8/hal_tick.c | 145 + .../TARGET_DISCO_L053C8/hal_tick.h | 60 + .../TARGET_DISCO_L053C8/stm32l053xx.h | 4189 +++++ .../TARGET_DISCO_L053C8/stm32l0xx.h | 233 + .../TARGET_DISCO_L053C8/system_stm32l0xx.c | 469 + .../TARGET_DISCO_L053C8/system_stm32l0xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S | 242 + .../TOOLCHAIN_ARM_MICRO/stm32l053r8.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l053xx.S | 215 + .../TOOLCHAIN_ARM_STD/stm32l053r8.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L053X8.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S | 299 + .../TOOLCHAIN_IAR/startup_stm32l053xx.S | 332 + .../TOOLCHAIN_IAR/stm32l053xx.icf | 30 + .../TARGET_NUCLEO_L053R8/cmsis.h | 38 + .../TARGET_NUCLEO_L053R8/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_L053R8/cmsis_nvic.h | 54 + .../TARGET_NUCLEO_L053R8/hal_tick.c | 145 + .../TARGET_NUCLEO_L053R8/hal_tick.h | 60 + .../TARGET_NUCLEO_L053R8/stm32l053xx.h | 4189 +++++ .../TARGET_NUCLEO_L053R8/stm32l0xx.h | 233 + .../TARGET_NUCLEO_L053R8/system_stm32l0xx.c | 469 + .../TARGET_NUCLEO_L053R8/system_stm32l0xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S | 252 + .../TOOLCHAIN_ARM_MICRO/stm32l073xz.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l073xx.S | 225 + .../TOOLCHAIN_ARM_STD/stm32l073xz.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L073XZ.ld | 153 + .../TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S | 311 + .../TOOLCHAIN_IAR/startup_stm32l073xx.S | 354 + .../TOOLCHAIN_IAR/stm32l073xx.icf | 30 + .../TARGET_NUCLEO_L073RZ/cmsis.h | 38 + .../TARGET_NUCLEO_L073RZ/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_L073RZ/cmsis_nvic.h | 54 + .../TARGET_NUCLEO_L073RZ/hal_tick.c | 145 + .../TARGET_NUCLEO_L073RZ/hal_tick.h | 60 + .../TARGET_NUCLEO_L073RZ/stm32l073xx.h | 4381 +++++ .../TARGET_NUCLEO_L073RZ/stm32l0xx.h | 233 + .../TARGET_NUCLEO_L073RZ/system_stm32l0xx.c | 469 + .../TARGET_NUCLEO_L073RZ/system_stm32l0xx.h | 123 + .../TARGET_STM32L0/stm32_hal_legacy.h | 2250 +++ .../TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c | 600 + .../TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h | 347 + .../TARGET_STM32L0/stm32l0xx_hal_adc.c | 1778 ++ .../TARGET_STM32L0/stm32l0xx_hal_adc.h | 966 ++ .../TARGET_STM32L0/stm32l0xx_hal_adc_ex.c | 317 + .../TARGET_STM32L0/stm32l0xx_hal_adc_ex.h | 129 + .../TARGET_STM32L0/stm32l0xx_hal_comp.c | 674 + .../TARGET_STM32L0/stm32l0xx_hal_comp.h | 557 + .../TARGET_STM32L0/stm32l0xx_hal_comp_ex.c | 120 + .../TARGET_STM32L0/stm32l0xx_hal_comp_ex.h | 91 + .../TARGET_STM32L0/stm32l0xx_hal_conf.h | 297 + .../TARGET_STM32L0/stm32l0xx_hal_cortex.c | 340 + .../TARGET_STM32L0/stm32l0xx_hal_cortex.h | 161 + .../TARGET_STM32L0/stm32l0xx_hal_crc.c | 515 + .../TARGET_STM32L0/stm32l0xx_hal_crc.h | 346 + .../TARGET_STM32L0/stm32l0xx_hal_crc_ex.c | 231 + .../TARGET_STM32L0/stm32l0xx_hal_crc_ex.h | 169 + .../TARGET_STM32L0/stm32l0xx_hal_cryp.c | 2164 +++ .../TARGET_STM32L0/stm32l0xx_hal_cryp.h | 424 + .../TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c | 116 + .../TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h | 100 + .../TARGET_STM32L0/stm32l0xx_hal_dac.c | 690 + .../TARGET_STM32L0/stm32l0xx_hal_dac.h | 432 + .../TARGET_STM32L0/stm32l0xx_hal_dac_ex.c | 1041 ++ .../TARGET_STM32L0/stm32l0xx_hal_dac_ex.h | 176 + .../TARGET_STM32L0/stm32l0xx_hal_def.h | 208 + .../TARGET_STM32L0/stm32l0xx_hal_dma.c | 773 + .../TARGET_STM32L0/stm32l0xx_hal_dma.h | 627 + .../TARGET_STM32L0/stm32l0xx_hal_firewall.c | 311 + .../TARGET_STM32L0/stm32l0xx_hal_firewall.h | 372 + .../TARGET_STM32L0/stm32l0xx_hal_flash.c | 736 + .../TARGET_STM32L0/stm32l0xx_hal_flash.h | 407 + .../TARGET_STM32L0/stm32l0xx_hal_flash_ex.c | 1065 ++ .../TARGET_STM32L0/stm32l0xx_hal_flash_ex.h | 692 + .../stm32l0xx_hal_flash_ramfunc.c | 472 + .../stm32l0xx_hal_flash_ramfunc.h | 113 + .../TARGET_STM32L0/stm32l0xx_hal_gpio.c | 543 + .../TARGET_STM32L0/stm32l0xx_hal_gpio.h | 330 + .../TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h | 1912 ++ .../TARGET_STM32L0/stm32l0xx_hal_i2c.c | 4110 +++++ .../TARGET_STM32L0/stm32l0xx_hal_i2c.h | 595 + .../TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c | 348 + .../TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h | 175 + .../TARGET_STM32L0/stm32l0xx_hal_i2s.c | 1409 ++ .../TARGET_STM32L0/stm32l0xx_hal_i2s.h | 479 + .../TARGET_STM32L0/stm32l0xx_hal_irda.c | 1465 ++ .../TARGET_STM32L0/stm32l0xx_hal_irda.h | 669 + .../TARGET_STM32L0/stm32l0xx_hal_irda_ex.h | 270 + .../TARGET_STM32L0/stm32l0xx_hal_iwdg.c | 409 + .../TARGET_STM32L0/stm32l0xx_hal_iwdg.h | 314 + .../TARGET_STM32L0/stm32l0xx_hal_lcd.c | 620 + .../TARGET_STM32L0/stm32l0xx_hal_lcd.h | 762 + .../TARGET_STM32L0/stm32l0xx_hal_lptim.c | 1602 ++ .../TARGET_STM32L0/stm32l0xx_hal_lptim.h | 661 + .../TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h | 127 + .../TARGET_STM32L0/stm32l0xx_hal_pcd.c | 1312 ++ .../TARGET_STM32L0/stm32l0xx_hal_pcd.h | 697 + .../TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c | 152 + .../TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h | 83 + .../TARGET_STM32L0/stm32l0xx_hal_pwr.c | 706 + .../TARGET_STM32L0/stm32l0xx_hal_pwr.h | 448 + .../TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c | 184 + .../TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h | 106 + .../TARGET_STM32L0/stm32l0xx_hal_rcc.c | 1370 ++ .../TARGET_STM32L0/stm32l0xx_hal_rcc.h | 1287 ++ .../TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c | 664 + .../TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h | 1487 ++ .../TARGET_STM32L0/stm32l0xx_hal_rng.c | 507 + .../TARGET_STM32L0/stm32l0xx_hal_rng.h | 362 + .../TARGET_STM32L0/stm32l0xx_hal_rtc.c | 1568 ++ .../TARGET_STM32L0/stm32l0xx_hal_rtc.h | 882 + .../TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c | 1863 ++ .../TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h | 993 ++ .../TARGET_STM32L0/stm32l0xx_hal_smartcard.c | 1292 ++ .../TARGET_STM32L0/stm32l0xx_hal_smartcard.h | 889 + .../stm32l0xx_hal_smartcard_ex.c | 185 + .../stm32l0xx_hal_smartcard_ex.h | 179 + .../TARGET_STM32L0/stm32l0xx_hal_smbus.c | 1851 ++ .../TARGET_STM32L0/stm32l0xx_hal_smbus.h | 567 + .../TARGET_STM32L0/stm32l0xx_hal_spi.c | 2389 +++ .../TARGET_STM32L0/stm32l0xx_hal_spi.h | 661 + .../TARGET_STM32L0/stm32l0xx_hal_tim.c | 5021 ++++++ .../TARGET_STM32L0/stm32l0xx_hal_tim.h | 1511 ++ .../TARGET_STM32L0/stm32l0xx_hal_tim_ex.c | 357 + .../TARGET_STM32L0/stm32l0xx_hal_tim_ex.h | 248 + .../TARGET_STM32L0/stm32l0xx_hal_tsc.c | 769 + .../TARGET_STM32L0/stm32l0xx_hal_tsc.h | 589 + .../TARGET_STM32L0/stm32l0xx_hal_uart.c | 1993 +++ .../TARGET_STM32L0/stm32l0xx_hal_uart.h | 1189 ++ .../TARGET_STM32L0/stm32l0xx_hal_uart_ex.c | 445 + .../TARGET_STM32L0/stm32l0xx_hal_uart_ex.h | 378 + .../TARGET_STM32L0/stm32l0xx_hal_usart.c | 1736 ++ .../TARGET_STM32L0/stm32l0xx_hal_usart.h | 684 + .../TARGET_STM32L0/stm32l0xx_hal_usart_ex.h | 233 + .../TARGET_STM32L0/stm32l0xx_hal_wwdg.c | 411 + .../TARGET_STM32L0/stm32l0xx_hal_wwdg.h | 349 + .../Release_Notes_stm32l1xx_hal.html | 972 ++ .../TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S | 325 + .../TOOLCHAIN_ARM_MICRO/stm32l152rc.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l152xc.S | 298 + .../TOOLCHAIN_ARM_STD/stm32l152rc.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L152XC.ld | 156 + .../TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S | 421 + .../TOOLCHAIN_IAR/startup_stm32l152xc.S | 536 + .../TOOLCHAIN_IAR/stm32l152xc.icf | 30 + .../TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h | 38 + .../TARGET_MOTE_L152RC/cmsis_nvic.c | 55 + .../TARGET_MOTE_L152RC/cmsis_nvic.h | 55 + .../TARGET_MOTE_L152RC/hal_tick.c | 121 + .../TARGET_MOTE_L152RC/hal_tick.h | 60 + .../TARGET_MOTE_L152RC/stm32l152xc.h | 5793 +++++++ .../TARGET_MOTE_L152RC/stm32l1xx.h | 247 + .../TARGET_MOTE_L152RC/system_stm32l1xx.c | 607 + .../TARGET_MOTE_L152RC/system_stm32l1xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S | 325 + .../TOOLCHAIN_ARM_MICRO/stm32l152re.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l152xe.S | 298 + .../TOOLCHAIN_ARM_STD/stm32l152re.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L152XE.ld | 156 + .../TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S | 434 + .../TOOLCHAIN_IAR/startup_stm32l152xe.S | 546 + .../TOOLCHAIN_IAR/stm32l152xe.icf | 31 + .../TARGET_NUCLEO_L152RE/cmsis.h | 38 + .../TARGET_NUCLEO_L152RE/cmsis_nvic.c | 55 + .../TARGET_NUCLEO_L152RE/cmsis_nvic.h | 55 + .../TARGET_NUCLEO_L152RE/hal_tick.c | 121 + .../TARGET_NUCLEO_L152RE/hal_tick.h | 60 + .../TARGET_NUCLEO_L152RE/stm32l152xe.h | 6016 +++++++ .../TARGET_NUCLEO_L152RE/stm32l1xx.h | 247 + .../TARGET_NUCLEO_L152RE/system_stm32l1xx.c | 604 + .../TARGET_NUCLEO_L152RE/system_stm32l1xx.h | 123 + .../TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S | 323 + .../TOOLCHAIN_ARM_MICRO/stm32l151rc.sct | 45 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 56 + .../TOOLCHAIN_ARM_STD/startup_stm32l151xc.S | 296 + .../TOOLCHAIN_ARM_STD/stm32l151rc.sct | 45 + .../TOOLCHAIN_ARM_STD/sys.cpp | 56 + .../TOOLCHAIN_GCC_ARM/STM32L151XC.ld | 157 + .../TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S | 418 + .../TARGET_STM32L1/TARGET_NZ32SC151/cmsis.h | 38 + .../TARGET_NZ32SC151/cmsis_nvic.c | 55 + .../TARGET_NZ32SC151/cmsis_nvic.h | 55 + .../TARGET_NZ32SC151/hal_tick.c | 121 + .../TARGET_NZ32SC151/hal_tick.h | 60 + .../TARGET_NZ32SC151/stm32l151xc.h | 5701 ++++++ .../TARGET_NZ32SC151/stm32l1xx.h | 261 + .../TARGET_NZ32SC151/system_stm32l1xx.c | 605 + .../TARGET_NZ32SC151/system_stm32l1xx.h | 123 + .../TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c | 454 + .../TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h | 955 + .../TARGET_STM32L1/stm32l1xx_hal_adc.c | 1759 ++ .../TARGET_STM32L1/stm32l1xx_hal_adc.h | 1107 ++ .../TARGET_STM32L1/stm32l1xx_hal_adc_ex.c | 849 + .../TARGET_STM32L1/stm32l1xx_hal_adc_ex.h | 693 + .../TARGET_STM32L1/stm32l1xx_hal_comp.c | 810 + .../TARGET_STM32L1/stm32l1xx_hal_comp.h | 520 + .../TARGET_STM32L1/stm32l1xx_hal_comp_ex.h | 336 + .../TARGET_STM32L1/stm32l1xx_hal_conf.h | 291 + .../TARGET_STM32L1/stm32l1xx_hal_cortex.c | 441 + .../TARGET_STM32L1/stm32l1xx_hal_cortex.h | 220 + .../TARGET_STM32L1/stm32l1xx_hal_crc.c | 339 + .../TARGET_STM32L1/stm32l1xx_hal_crc.h | 192 + .../TARGET_STM32L1/stm32l1xx_hal_cryp.c | 2111 +++ .../TARGET_STM32L1/stm32l1xx_hal_cryp.h | 411 + .../TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c | 118 + .../TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h | 98 + .../TARGET_STM32L1/stm32l1xx_hal_dac.c | 963 ++ .../TARGET_STM32L1/stm32l1xx_hal_dac.h | 385 + .../TARGET_STM32L1/stm32l1xx_hal_dac_ex.c | 382 + .../TARGET_STM32L1/stm32l1xx_hal_dac_ex.h | 205 + .../TARGET_STM32L1/stm32l1xx_hal_def.h | 195 + .../TARGET_STM32L1/stm32l1xx_hal_dma.c | 707 + .../TARGET_STM32L1/stm32l1xx_hal_dma.h | 444 + .../TARGET_STM32L1/stm32l1xx_hal_dma_ex.h | 248 + .../TARGET_STM32L1/stm32l1xx_hal_flash.c | 490 + .../TARGET_STM32L1/stm32l1xx_hal_flash.h | 385 + .../TARGET_STM32L1/stm32l1xx_hal_flash_ex.c | 1952 +++ .../TARGET_STM32L1/stm32l1xx_hal_flash_ex.h | 975 ++ .../stm32l1xx_hal_flash_ramfunc.c | 545 + .../stm32l1xx_hal_flash_ramfunc.h | 130 + .../TARGET_STM32L1/stm32l1xx_hal_gpio.c | 540 + .../TARGET_STM32L1/stm32l1xx_hal_gpio.h | 331 + .../TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h | 260 + .../TARGET_STM32L1/stm32l1xx_hal_i2c.c | 3635 ++++ .../TARGET_STM32L1/stm32l1xx_hal_i2c.h | 538 + .../TARGET_STM32L1/stm32l1xx_hal_i2s.c | 1384 ++ .../TARGET_STM32L1/stm32l1xx_hal_i2s.h | 454 + .../TARGET_STM32L1/stm32l1xx_hal_irda.c | 1571 ++ .../TARGET_STM32L1/stm32l1xx_hal_irda.h | 535 + .../TARGET_STM32L1/stm32l1xx_hal_iwdg.c | 360 + .../TARGET_STM32L1/stm32l1xx_hal_iwdg.h | 291 + .../TARGET_STM32L1/stm32l1xx_hal_lcd.c | 610 + .../TARGET_STM32L1/stm32l1xx_hal_lcd.h | 763 + .../TARGET_STM32L1/stm32l1xx_hal_nor.c | 838 + .../TARGET_STM32L1/stm32l1xx_hal_nor.h | 307 + .../TARGET_STM32L1/stm32l1xx_hal_opamp.c | 1004 ++ .../TARGET_STM32L1/stm32l1xx_hal_opamp.h | 533 + .../TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c | 757 + .../TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h | 225 + .../TARGET_STM32L1/stm32l1xx_hal_pcd.c | 1345 ++ .../TARGET_STM32L1/stm32l1xx_hal_pcd.h | 833 + .../TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c | 147 + .../TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h | 89 + .../TARGET_STM32L1/stm32l1xx_hal_pwr.c | 612 + .../TARGET_STM32L1/stm32l1xx_hal_pwr.h | 431 + .../TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c | 168 + .../TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h | 135 + .../TARGET_STM32L1/stm32l1xx_hal_rcc.c | 1313 ++ .../TARGET_STM32L1/stm32l1xx_hal_rcc.h | 1227 ++ .../TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c | 277 + .../TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h | 573 + .../TARGET_STM32L1/stm32l1xx_hal_rtc.c | 902 + .../TARGET_STM32L1/stm32l1xx_hal_rtc.h | 641 + .../TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c | 2482 +++ .../TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h | 973 ++ .../TARGET_STM32L1/stm32l1xx_hal_sd.c | 3439 ++++ .../TARGET_STM32L1/stm32l1xx_hal_sd.h | 705 + .../TARGET_STM32L1/stm32l1xx_hal_smartcard.c | 1411 ++ .../TARGET_STM32L1/stm32l1xx_hal_smartcard.h | 587 + .../TARGET_STM32L1/stm32l1xx_hal_spi.c | 2256 +++ .../TARGET_STM32L1/stm32l1xx_hal_spi.h | 556 + .../TARGET_STM32L1/stm32l1xx_hal_spi_ex.c | 153 + .../TARGET_STM32L1/stm32l1xx_hal_spi_ex.h | 106 + .../TARGET_STM32L1/stm32l1xx_hal_sram.c | 681 + .../TARGET_STM32L1/stm32l1xx_hal_sram.h | 202 + .../TARGET_STM32L1/stm32l1xx_hal_tim.c | 5039 ++++++ .../TARGET_STM32L1/stm32l1xx_hal_tim.h | 1508 ++ .../TARGET_STM32L1/stm32l1xx_hal_tim_ex.c | 260 + .../TARGET_STM32L1/stm32l1xx_hal_tim_ex.h | 212 + .../TARGET_STM32L1/stm32l1xx_hal_uart.c | 1974 +++ .../TARGET_STM32L1/stm32l1xx_hal_uart.h | 624 + .../TARGET_STM32L1/stm32l1xx_hal_usart.c | 1879 ++ .../TARGET_STM32L1/stm32l1xx_hal_usart.h | 579 + .../TARGET_STM32L1/stm32l1xx_hal_wwdg.c | 444 + .../TARGET_STM32L1/stm32l1xx_hal_wwdg.h | 310 + .../TARGET_STM32L1/stm32l1xx_ll_fsmc.c | 359 + .../TARGET_STM32L1/stm32l1xx_ll_fsmc.h | 567 + .../TARGET_STM32L1/stm32l1xx_ll_sdmmc.c | 519 + .../TARGET_STM32L1/stm32l1xx_ll_sdmmc.h | 907 + .../TOOLCHAIN_ARM_MICRO/efm32gg.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_efm32gg.S | 279 + .../TOOLCHAIN_ARM_STD/efm32gg.sct | 15 + .../TOOLCHAIN_ARM_STD/startup_efm32gg.S | 288 + .../TOOLCHAIN_GCC_ARM/efm32gg.ld | 160 + .../TOOLCHAIN_GCC_ARM/startup_efm32gg.S | 233 + .../TARGET_EFM32GG_STK3700/cmsis.h | 13 + .../TARGET_EFM32GG_STK3700/cmsis_nvic.c | 47 + .../TARGET_EFM32GG_STK3700/cmsis_nvic.h | 26 + .../TARGET_EFM32GG_STK3700/efm32gg990f1024.h | 477 + .../TARGET_EFM32GG_STK3700/efm32gg_acmp.h | 331 + .../TARGET_EFM32GG_STK3700/efm32gg_adc.h | 670 + .../TARGET_EFM32GG_STK3700/efm32gg_aes.h | 239 + .../TARGET_EFM32GG_STK3700/efm32gg_af_pins.h | 204 + .../TARGET_EFM32GG_STK3700/efm32gg_af_ports.h | 204 + .../TARGET_EFM32GG_STK3700/efm32gg_burtc.h | 377 + .../efm32gg_burtc_ret.h | 39 + .../efm32gg_calibrate.h | 43 + .../TARGET_EFM32GG_STK3700/efm32gg_cmu.h | 1247 ++ .../TARGET_EFM32GG_STK3700/efm32gg_dac.h | 792 + .../TARGET_EFM32GG_STK3700/efm32gg_devinfo.h | 154 + .../TARGET_EFM32GG_STK3700/efm32gg_dma.h | 1629 ++ .../TARGET_EFM32GG_STK3700/efm32gg_dma_ch.h | 39 + .../efm32gg_dma_descriptor.h | 45 + .../TARGET_EFM32GG_STK3700/efm32gg_dmactrl.h | 136 + .../TARGET_EFM32GG_STK3700/efm32gg_dmareq.h | 99 + .../TARGET_EFM32GG_STK3700/efm32gg_ebi.h | 1460 ++ .../TARGET_EFM32GG_STK3700/efm32gg_emu.h | 357 + .../TARGET_EFM32GG_STK3700/efm32gg_etm.h | 782 + .../TARGET_EFM32GG_STK3700/efm32gg_gpio.h | 1204 ++ .../TARGET_EFM32GG_STK3700/efm32gg_gpio_p.h | 47 + .../TARGET_EFM32GG_STK3700/efm32gg_i2c.h | 701 + .../TARGET_EFM32GG_STK3700/efm32gg_lcd.h | 595 + .../TARGET_EFM32GG_STK3700/efm32gg_lesense.h | 1925 +++ .../efm32gg_lesense_buf.h | 39 + .../efm32gg_lesense_ch.h | 43 + .../efm32gg_lesense_st.h | 40 + .../TARGET_EFM32GG_STK3700/efm32gg_letimer.h | 408 + .../TARGET_EFM32GG_STK3700/efm32gg_leuart.h | 699 + .../TARGET_EFM32GG_STK3700/efm32gg_msc.h | 463 + .../TARGET_EFM32GG_STK3700/efm32gg_pcnt.h | 417 + .../TARGET_EFM32GG_STK3700/efm32gg_prs.h | 452 + .../TARGET_EFM32GG_STK3700/efm32gg_prs_ch.h | 39 + .../efm32gg_prs_signals.h | 123 + .../TARGET_EFM32GG_STK3700/efm32gg_rmu.h | 158 + .../TARGET_EFM32GG_STK3700/efm32gg_romtable.h | 68 + .../TARGET_EFM32GG_STK3700/efm32gg_rtc.h | 214 + .../TARGET_EFM32GG_STK3700/efm32gg_timer.h | 965 ++ .../TARGET_EFM32GG_STK3700/efm32gg_timer_cc.h | 42 + .../TARGET_EFM32GG_STK3700/efm32gg_uart.h | 1117 ++ .../TARGET_EFM32GG_STK3700/efm32gg_usart.h | 1149 ++ .../TARGET_EFM32GG_STK3700/efm32gg_usb.h | 2661 +++ .../TARGET_EFM32GG_STK3700/efm32gg_usb_diep.h | 47 + .../TARGET_EFM32GG_STK3700/efm32gg_usb_doep.h | 46 + .../TARGET_EFM32GG_STK3700/efm32gg_usb_hc.h | 46 + .../TARGET_EFM32GG_STK3700/efm32gg_vcmp.h | 196 + .../TARGET_EFM32GG_STK3700/efm32gg_wdog.h | 132 + .../TARGET_EFM32GG_STK3700/em_device.h | 171 + .../TARGET_EFM32GG_STK3700/system_efm32gg.c | 385 + .../TARGET_EFM32GG_STK3700/system_efm32gg.h | 138 + .../TOOLCHAIN_ARM_MICRO/efm32hg.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_efm32hg.S | 202 + .../TOOLCHAIN_GCC_ARM/efm32hg.ld | 167 + .../TOOLCHAIN_GCC_ARM/startup_efm32hg.S | 194 + .../TARGET_EFM32HG_STK3400/arm_math.h | 7306 ++++++++ .../TARGET_EFM32HG_STK3400/cmsis.h | 13 + .../TARGET_EFM32HG_STK3400/cmsis_nvic.c | 47 + .../TARGET_EFM32HG_STK3400/cmsis_nvic.h | 26 + .../TARGET_EFM32HG_STK3400/efm32hg322f64.h | 399 + .../TARGET_EFM32HG_STK3400/efm32hg_acmp.h | 329 + .../TARGET_EFM32HG_STK3400/efm32hg_adc.h | 655 + .../TARGET_EFM32HG_STK3400/efm32hg_aes.h | 193 + .../TARGET_EFM32HG_STK3400/efm32hg_af_pins.h | 83 + .../TARGET_EFM32HG_STK3400/efm32hg_af_ports.h | 83 + .../efm32hg_calibrate.h | 43 + .../TARGET_EFM32HG_STK3400/efm32hg_cmu.h | 1202 ++ .../TARGET_EFM32HG_STK3400/efm32hg_devinfo.h | 160 + .../TARGET_EFM32HG_STK3400/efm32hg_dma.h | 888 + .../TARGET_EFM32HG_STK3400/efm32hg_dma_ch.h | 39 + .../efm32hg_dma_descriptor.h | 45 + .../TARGET_EFM32HG_STK3400/efm32hg_dmactrl.h | 136 + .../TARGET_EFM32HG_STK3400/efm32hg_dmareq.h | 72 + .../TARGET_EFM32HG_STK3400/efm32hg_emu.h | 102 + .../TARGET_EFM32HG_STK3400/efm32hg_gpio.h | 1150 ++ .../TARGET_EFM32HG_STK3400/efm32hg_gpio_p.h | 47 + .../TARGET_EFM32HG_STK3400/efm32hg_i2c.h | 701 + .../TARGET_EFM32HG_STK3400/efm32hg_idac.h | 148 + .../TARGET_EFM32HG_STK3400/efm32hg_leuart.h | 689 + .../TARGET_EFM32HG_STK3400/efm32hg_msc.h | 412 + .../TARGET_EFM32HG_STK3400/efm32hg_mtb.h | 119 + .../TARGET_EFM32HG_STK3400/efm32hg_pcnt.h | 482 + .../TARGET_EFM32HG_STK3400/efm32hg_prs.h | 354 + .../TARGET_EFM32HG_STK3400/efm32hg_prs_ch.h | 39 + .../efm32hg_prs_signals.h | 87 + .../TARGET_EFM32HG_STK3400/efm32hg_rmu.h | 128 + .../TARGET_EFM32HG_STK3400/efm32hg_romtable.h | 68 + .../TARGET_EFM32HG_STK3400/efm32hg_rtc.h | 214 + .../TARGET_EFM32HG_STK3400/efm32hg_timer.h | 951 + .../TARGET_EFM32HG_STK3400/efm32hg_timer_cc.h | 42 + .../TARGET_EFM32HG_STK3400/efm32hg_usart.h | 1145 ++ .../TARGET_EFM32HG_STK3400/efm32hg_usb.h | 1793 ++ .../TARGET_EFM32HG_STK3400/efm32hg_usb_diep.h | 46 + .../TARGET_EFM32HG_STK3400/efm32hg_usb_doep.h | 45 + .../TARGET_EFM32HG_STK3400/efm32hg_vcmp.h | 196 + .../TARGET_EFM32HG_STK3400/efm32hg_wdog.h | 132 + .../TARGET_EFM32HG_STK3400/em_device.h | 111 + .../TARGET_EFM32HG_STK3400/system_efm32hg.c | 383 + .../TARGET_EFM32HG_STK3400/system_efm32hg.h | 116 + .../TOOLCHAIN_ARM_MICRO/efm32lg.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_efm32lg.S | 279 + .../TOOLCHAIN_ARM_STD/efm32lg.sct | 15 + .../TOOLCHAIN_ARM_STD/startup_efm32lg.S | 298 + .../TOOLCHAIN_GCC_ARM/efm32lg.ld | 160 + .../TOOLCHAIN_GCC_ARM/startup_efm32lg.S | 233 + .../TARGET_EFM32LG_STK3600/cmsis.h | 13 + .../TARGET_EFM32LG_STK3600/cmsis_nvic.c | 47 + .../TARGET_EFM32LG_STK3600/cmsis_nvic.h | 26 + .../TARGET_EFM32LG_STK3600/efm32lg990f256.h | 1694 ++ .../TARGET_EFM32LG_STK3600/efm32lg_acmp.h | 331 + .../TARGET_EFM32LG_STK3600/efm32lg_adc.h | 670 + .../TARGET_EFM32LG_STK3600/efm32lg_aes.h | 239 + .../TARGET_EFM32LG_STK3600/efm32lg_af_pins.h | 204 + .../TARGET_EFM32LG_STK3600/efm32lg_af_ports.h | 204 + .../TARGET_EFM32LG_STK3600/efm32lg_burtc.h | 377 + .../efm32lg_burtc_ret.h | 39 + .../efm32lg_calibrate.h | 43 + .../TARGET_EFM32LG_STK3600/efm32lg_cmu.h | 1247 ++ .../TARGET_EFM32LG_STK3600/efm32lg_dac.h | 792 + .../TARGET_EFM32LG_STK3600/efm32lg_devinfo.h | 154 + .../TARGET_EFM32LG_STK3600/efm32lg_dma.h | 1629 ++ .../TARGET_EFM32LG_STK3600/efm32lg_dma_ch.h | 39 + .../efm32lg_dma_descriptor.h | 45 + .../TARGET_EFM32LG_STK3600/efm32lg_dmactrl.h | 136 + .../TARGET_EFM32LG_STK3600/efm32lg_dmareq.h | 99 + .../TARGET_EFM32LG_STK3600/efm32lg_ebi.h | 1460 ++ .../TARGET_EFM32LG_STK3600/efm32lg_emu.h | 344 + .../TARGET_EFM32LG_STK3600/efm32lg_etm.h | 782 + .../TARGET_EFM32LG_STK3600/efm32lg_gpio.h | 1204 ++ .../TARGET_EFM32LG_STK3600/efm32lg_gpio_p.h | 47 + .../TARGET_EFM32LG_STK3600/efm32lg_i2c.h | 701 + .../TARGET_EFM32LG_STK3600/efm32lg_lcd.h | 595 + .../TARGET_EFM32LG_STK3600/efm32lg_lesense.h | 1925 +++ .../efm32lg_lesense_buf.h | 39 + .../efm32lg_lesense_ch.h | 43 + .../efm32lg_lesense_st.h | 40 + .../TARGET_EFM32LG_STK3600/efm32lg_letimer.h | 408 + .../TARGET_EFM32LG_STK3600/efm32lg_leuart.h | 699 + .../TARGET_EFM32LG_STK3600/efm32lg_msc.h | 433 + .../TARGET_EFM32LG_STK3600/efm32lg_pcnt.h | 417 + .../TARGET_EFM32LG_STK3600/efm32lg_prs.h | 452 + .../TARGET_EFM32LG_STK3600/efm32lg_prs_ch.h | 39 + .../efm32lg_prs_signals.h | 123 + .../TARGET_EFM32LG_STK3600/efm32lg_rmu.h | 158 + .../TARGET_EFM32LG_STK3600/efm32lg_romtable.h | 68 + .../TARGET_EFM32LG_STK3600/efm32lg_rtc.h | 214 + .../TARGET_EFM32LG_STK3600/efm32lg_timer.h | 965 ++ .../TARGET_EFM32LG_STK3600/efm32lg_timer_cc.h | 42 + .../TARGET_EFM32LG_STK3600/efm32lg_uart.h | 1117 ++ .../TARGET_EFM32LG_STK3600/efm32lg_usart.h | 1149 ++ .../TARGET_EFM32LG_STK3600/efm32lg_usb.h | 2661 +++ .../TARGET_EFM32LG_STK3600/efm32lg_usb_diep.h | 47 + .../TARGET_EFM32LG_STK3600/efm32lg_usb_doep.h | 46 + .../TARGET_EFM32LG_STK3600/efm32lg_usb_hc.h | 46 + .../TARGET_EFM32LG_STK3600/efm32lg_vcmp.h | 196 + .../TARGET_EFM32LG_STK3600/efm32lg_wdog.h | 132 + .../TARGET_EFM32LG_STK3600/em_device.h | 231 + .../TARGET_EFM32LG_STK3600/system_efm32lg.c | 385 + .../TARGET_EFM32LG_STK3600/system_efm32lg.h | 138 + .../TOOLCHAIN_ARM_MICRO/efm32wg.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_efm32wg.S | 282 + .../TOOLCHAIN_ARM_STD/efm32wg.sct | 15 + .../TOOLCHAIN_ARM_STD/startup_efm32wg.S | 301 + .../TOOLCHAIN_GCC_ARM/efm32wg.ld | 160 + .../TOOLCHAIN_GCC_ARM/startup_efm32wg.S | 235 + .../TARGET_EFM32WG_STK3800/cmsis.h | 13 + .../TARGET_EFM32WG_STK3800/cmsis_nvic.c | 47 + .../TARGET_EFM32WG_STK3800/cmsis_nvic.h | 26 + .../TARGET_EFM32WG_STK3800/efm32wg990f256.h | 483 + .../TARGET_EFM32WG_STK3800/efm32wg_acmp.h | 331 + .../TARGET_EFM32WG_STK3800/efm32wg_adc.h | 670 + .../TARGET_EFM32WG_STK3800/efm32wg_aes.h | 239 + .../TARGET_EFM32WG_STK3800/efm32wg_af_pins.h | 204 + .../TARGET_EFM32WG_STK3800/efm32wg_af_ports.h | 204 + .../TARGET_EFM32WG_STK3800/efm32wg_burtc.h | 377 + .../efm32wg_burtc_ret.h | 39 + .../efm32wg_calibrate.h | 43 + .../TARGET_EFM32WG_STK3800/efm32wg_cmu.h | 1247 ++ .../TARGET_EFM32WG_STK3800/efm32wg_dac.h | 792 + .../TARGET_EFM32WG_STK3800/efm32wg_devinfo.h | 154 + .../TARGET_EFM32WG_STK3800/efm32wg_dma.h | 1629 ++ .../TARGET_EFM32WG_STK3800/efm32wg_dma_ch.h | 39 + .../efm32wg_dma_descriptor.h | 45 + .../TARGET_EFM32WG_STK3800/efm32wg_dmactrl.h | 136 + .../TARGET_EFM32WG_STK3800/efm32wg_dmareq.h | 99 + .../TARGET_EFM32WG_STK3800/efm32wg_ebi.h | 1460 ++ .../TARGET_EFM32WG_STK3800/efm32wg_emu.h | 344 + .../TARGET_EFM32WG_STK3800/efm32wg_etm.h | 782 + .../TARGET_EFM32WG_STK3800/efm32wg_fpueh.h | 188 + .../TARGET_EFM32WG_STK3800/efm32wg_gpio.h | 1204 ++ .../TARGET_EFM32WG_STK3800/efm32wg_gpio_p.h | 47 + .../TARGET_EFM32WG_STK3800/efm32wg_i2c.h | 701 + .../TARGET_EFM32WG_STK3800/efm32wg_lcd.h | 595 + .../TARGET_EFM32WG_STK3800/efm32wg_lesense.h | 1925 +++ .../efm32wg_lesense_buf.h | 39 + .../efm32wg_lesense_ch.h | 43 + .../efm32wg_lesense_st.h | 40 + .../TARGET_EFM32WG_STK3800/efm32wg_letimer.h | 408 + .../TARGET_EFM32WG_STK3800/efm32wg_leuart.h | 699 + .../TARGET_EFM32WG_STK3800/efm32wg_msc.h | 433 + .../TARGET_EFM32WG_STK3800/efm32wg_pcnt.h | 417 + .../TARGET_EFM32WG_STK3800/efm32wg_prs.h | 452 + .../TARGET_EFM32WG_STK3800/efm32wg_prs_ch.h | 39 + .../efm32wg_prs_signals.h | 122 + .../TARGET_EFM32WG_STK3800/efm32wg_rmu.h | 158 + .../TARGET_EFM32WG_STK3800/efm32wg_romtable.h | 68 + .../TARGET_EFM32WG_STK3800/efm32wg_rtc.h | 214 + .../TARGET_EFM32WG_STK3800/efm32wg_timer.h | 965 ++ .../TARGET_EFM32WG_STK3800/efm32wg_timer_cc.h | 42 + .../TARGET_EFM32WG_STK3800/efm32wg_uart.h | 1127 ++ .../TARGET_EFM32WG_STK3800/efm32wg_usart.h | 1159 ++ .../TARGET_EFM32WG_STK3800/efm32wg_usb.h | 2661 +++ .../TARGET_EFM32WG_STK3800/efm32wg_usb_diep.h | 47 + .../TARGET_EFM32WG_STK3800/efm32wg_usb_doep.h | 46 + .../TARGET_EFM32WG_STK3800/efm32wg_usb_hc.h | 46 + .../TARGET_EFM32WG_STK3800/efm32wg_vcmp.h | 196 + .../TARGET_EFM32WG_STK3800/efm32wg_wdog.h | 132 + .../TARGET_EFM32WG_STK3800/em_device.h | 231 + .../TARGET_EFM32WG_STK3800/system_efm32wg.c | 388 + .../TARGET_EFM32WG_STK3800/system_efm32wg.h | 139 + .../TOOLCHAIN_ARM_MICRO/efm32zg.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_efm32zg.S | 193 + .../TOOLCHAIN_GCC_ARM/efm32zg.ld | 160 + .../TOOLCHAIN_GCC_ARM/startup_efm32zg.S | 185 + .../TARGET_EFM32ZG_STK3200/arm_math.h | 7306 ++++++++ .../TARGET_EFM32ZG_STK3200/cmsis.h | 13 + .../TARGET_EFM32ZG_STK3200/cmsis_nvic.c | 47 + .../TARGET_EFM32ZG_STK3200/cmsis_nvic.h | 26 + .../TARGET_EFM32ZG_STK3200/efm32zg222f32.h | 362 + .../TARGET_EFM32ZG_STK3200/efm32zg_acmp.h | 327 + .../TARGET_EFM32ZG_STK3200/efm32zg_adc.h | 647 + .../TARGET_EFM32ZG_STK3200/efm32zg_aes.h | 193 + .../TARGET_EFM32ZG_STK3200/efm32zg_af_pins.h | 72 + .../TARGET_EFM32ZG_STK3200/efm32zg_af_ports.h | 72 + .../efm32zg_calibrate.h | 43 + .../TARGET_EFM32ZG_STK3200/efm32zg_cmu.h | 977 ++ .../TARGET_EFM32ZG_STK3200/efm32zg_devinfo.h | 139 + .../TARGET_EFM32ZG_STK3200/efm32zg_dma.h | 691 + .../TARGET_EFM32ZG_STK3200/efm32zg_dma_ch.h | 39 + .../efm32zg_dma_descriptor.h | 45 + .../TARGET_EFM32ZG_STK3200/efm32zg_dmactrl.h | 136 + .../TARGET_EFM32ZG_STK3200/efm32zg_dmareq.h | 65 + .../TARGET_EFM32ZG_STK3200/efm32zg_emu.h | 102 + .../TARGET_EFM32ZG_STK3200/efm32zg_gpio.h | 1144 ++ .../TARGET_EFM32ZG_STK3200/efm32zg_gpio_p.h | 47 + .../TARGET_EFM32ZG_STK3200/efm32zg_i2c.h | 701 + .../TARGET_EFM32ZG_STK3200/efm32zg_idac.h | 144 + .../TARGET_EFM32ZG_STK3200/efm32zg_leuart.h | 683 + .../TARGET_EFM32ZG_STK3200/efm32zg_msc.h | 412 + .../TARGET_EFM32ZG_STK3200/efm32zg_pcnt.h | 468 + .../TARGET_EFM32ZG_STK3200/efm32zg_prs.h | 258 + .../TARGET_EFM32ZG_STK3200/efm32zg_prs_ch.h | 39 + .../efm32zg_prs_signals.h | 78 + .../TARGET_EFM32ZG_STK3200/efm32zg_rmu.h | 128 + .../TARGET_EFM32ZG_STK3200/efm32zg_romtable.h | 68 + .../TARGET_EFM32ZG_STK3200/efm32zg_rtc.h | 214 + .../TARGET_EFM32ZG_STK3200/efm32zg_timer.h | 661 + .../TARGET_EFM32ZG_STK3200/efm32zg_timer_cc.h | 42 + .../TARGET_EFM32ZG_STK3200/efm32zg_usart.h | 1123 ++ .../TARGET_EFM32ZG_STK3200/efm32zg_vcmp.h | 196 + .../TARGET_EFM32ZG_STK3200/efm32zg_wdog.h | 132 + .../TARGET_EFM32ZG_STK3200/em_device.h | 99 + .../TARGET_EFM32ZG_STK3200/system_efm32zg.c | 360 + .../TARGET_EFM32ZG_STK3200/system_efm32zg.h | 111 + .../TOOLCHAIN_ARM_MICRO/W7500.sct | 15 + .../TOOLCHAIN_ARM_MICRO/startup_W7500x.S | 213 + .../TOOLCHAIN_ARM_MICRO/sys.cpp | 31 + .../TOOLCHAIN_ARM_STD/W7500.sct | 15 + .../TOOLCHAIN_ARM_STD/startup_W7500x.S | 186 + .../TOOLCHAIN_ARM_STD/sys.cpp | 31 + .../TOOLCHAIN_GCC_ARM/W7500.ld | 152 + .../TOOLCHAIN_GCC_ARM/startup_W7500.S | 259 + .../TARGET_WIZwiki_W7500/W7500x.h | 1168 ++ .../TARGET_WIZwiki_W7500/cmsis.h | 38 + .../TARGET_WIZwiki_W7500/cmsis_nvic.c | 47 + .../TARGET_WIZwiki_W7500/cmsis_nvic.h | 51 + .../TARGET_WIZwiki_W7500/system_W7500x.c | 104 + .../TARGET_WIZwiki_W7500/system_W7500x.h | 84 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c | 54 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h | 59 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h | 16 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c | 276 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h | 145 + .../TARGET_W7500x/W7500x_dualtimer.c | 205 + .../TARGET_W7500x/W7500x_dualtimer.h | 96 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c | 157 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h | 86 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c | 288 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h | 134 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c | 589 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h | 236 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c | 905 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h | 289 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c | 370 + .../TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h | 289 + .../TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S | 94 + targets/cmsis/TOOLCHAIN_IAR/cmain.S | 81 + targets/cmsis/core_ca9.h | 271 + targets/cmsis/core_caFunc.h | 1161 ++ targets/cmsis/core_caInstr.h | 45 + targets/cmsis/core_ca_mmu.h | 848 + targets/cmsis/core_cm0.h | 682 + targets/cmsis/core_cm0plus.h | 793 + targets/cmsis/core_cm3.h | 1627 ++ targets/cmsis/core_cm4.h | 1772 ++ targets/cmsis/core_cm4_simd.h | 673 + targets/cmsis/core_cm7.h | 2397 +++ targets/cmsis/core_cmFunc.h | 636 + targets/cmsis/core_cmInstr.h | 688 + targets/cmsis/core_cmSimd.h | 697 + .../TARGET_MPS2/PeripheralNames.h | 79 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h | 168 + .../TARGET_ARM_SSG/TARGET_MPS2/PortNames.h | 31 + .../TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c | 451 + .../TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.h | 65 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c | 90 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.h | 34 + .../TARGET_MPS2/SDK/mps2_ethernet_api.c | 127 + .../TARGET_MPS2/SDK/mps2_ethernet_api.h | 57 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/device.h | 64 + .../TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c | 164 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c | 124 + .../TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c | 241 + .../TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h | 55 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c | 415 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h | 74 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c | 28 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/port_api.c | 68 + .../TARGET_ARM_SSG/TARGET_MPS2/serial_api.c | 230 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c | 227 + .../hal/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h | 174 + .../TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c | 84 + .../TARGET_SAM21/PeripheralNames.h | 156 + .../TARGET_SAM21/PeripheralPins.h | 40 + .../hal/TARGET_Atmel/TARGET_SAM21/PinNames.h | 101 + .../hal/TARGET_Atmel/TARGET_SAM21/PortNames.h | 31 + .../SAMD21_XPLAINED_PRO/mbed_overrides.c | 26 + .../SAMD21_XPLAINED_PRO/samd21_xplained_pro.h | 662 + .../TARGET_SAM21/TARGET_SAMD21J18A/device.h | 62 + .../TARGET_SAMR21G18A/PeripheralPins.c | 154 + .../SAMR21_XPLAINED_PRO/mbed_overrides.c | 32 + .../SAMR21_XPLAINED_PRO/samr21_xplained_pro.h | 475 + .../TARGET_SAM21/TARGET_SAMR21G18A/device.h | 62 + .../TARGET_Atmel/TARGET_SAM21/analogin_api.c | 181 + .../hal/TARGET_Atmel/TARGET_SAM21/dma_api.c | 372 + .../TARGET_Atmel/TARGET_SAM21/dma_api_HAL.h | 106 + .../TARGET_SAM21/drivers/adc/adc.h | 1037 ++ .../drivers/adc/adc_sam_d_r/adc.c | 638 + .../drivers/adc/adc_sam_d_r/adc_feature.h | 680 + .../TARGET_SAM21/drivers/dma/dma.c | 607 + .../TARGET_SAM21/drivers/dma/dma.h | 806 + .../TARGET_SAM21/drivers/dma/dma_crc.h | 185 + .../drivers/dma/quick_start/qs_dma_basic.h | 112 + .../TARGET_SAM21/drivers/extint/extint.h | 665 + .../drivers/extint/extint_callback.c | 185 + .../drivers/extint/extint_callback.h | 62 + .../drivers/extint/extint_sam_d_r/extint.c | 381 + .../TARGET_SAM21/drivers/port/port.c | 64 + .../TARGET_SAM21/drivers/port/port.h | 745 + .../drivers/port/quick_start/qs_port_basic.h | 65 + .../TARGET_SAM21/drivers/rtc/rtc_count.h | 1155 ++ .../drivers/rtc/rtc_sam_d_r/rtc_count.c | 728 + .../drivers/sercom/i2c/i2c_common.h | 524 + .../drivers/sercom/i2c/i2c_master.h | 557 + .../i2c_samd21_r21_d10_d11_l21/i2c_master.c | 831 + .../i2c_samd21_r21_d10_d11_l21/i2c_slave.c | 674 + .../drivers/sercom/i2c/i2c_slave.h | 617 + .../qs_i2c_master_basic_use.h | 75 + .../qs_i2c_master_dma.h | 127 + .../qs_i2c_slave_basic_use.h | 66 + .../quick_start_slave_dma/qs_i2c_slave_dma.h | 116 + .../TARGET_SAM21/drivers/sercom/sercom.c | 251 + .../TARGET_SAM21/drivers/sercom/sercom.h | 90 + .../drivers/sercom/sercom_interrupt.c | 95 + .../drivers/sercom/sercom_interrupt.h | 27 + .../drivers/sercom/sercom_pinout.h | 137 + .../TARGET_SAM21/drivers/sercom/usart/usart.c | 679 + .../TARGET_SAM21/drivers/sercom/usart/usart.h | 1221 ++ .../drivers/sercom/usart/usart_interrupt.c | 614 + .../drivers/sercom/usart/usart_interrupt.h | 131 + .../TARGET_SAM21/drivers/system/clock/clock.h | 8 + .../system/clock/clock_samd21_r21/clock.c | 958 + .../clock_samd21_r21/clock_config_check.h | 380 + .../clock/clock_samd21_r21/clock_feature.h | 1446 ++ .../system/clock/clock_samd21_r21/gclk.c | 476 + .../TARGET_SAM21/drivers/system/clock/gclk.h | 260 + .../system/interrupt/system_interrupt.c | 172 + .../system/interrupt/system_interrupt.h | 395 + .../system_interrupt_features.h | 136 + .../drivers/system/pinmux/pinmux.c | 266 + .../drivers/system/pinmux/pinmux.h | 631 + .../pinmux/quick_start/qs_pinmux_basic.h | 53 + .../system/power/power_sam_d_r/power.h | 179 + .../system/reset/reset_sam_d_r/reset.h | 74 + .../TARGET_SAM21/drivers/system/system.c | 59 + .../TARGET_SAM21/drivers/system/system.h | 643 + .../TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h | 1669 ++ .../TARGET_SAM21/drivers/tc/tc_interrupt.c | 148 + .../TARGET_SAM21/drivers/tc/tc_interrupt.h | 128 + .../TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c | 638 + .../hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c | 94 + .../TARGET_Atmel/TARGET_SAM21/gpio_irq_api.c | 150 + .../TARGET_Atmel/TARGET_SAM21/gpio_object.h | 65 + .../hal/TARGET_Atmel/TARGET_SAM21/objects.h | 110 + .../hal/TARGET_Atmel/TARGET_SAM21/pinmap.c | 108 + .../TARGET_SAM21/pinmap_function.c | 221 + .../TARGET_SAM21/pinmap_function.h | 82 + .../hal/TARGET_Atmel/TARGET_SAM21/port_api.c | 39 + .../hal/TARGET_Atmel/TARGET_SAM21/rtc_api.c | 118 + .../TARGET_Atmel/TARGET_SAM21/sercom_dma.c | 95 + .../TARGET_Atmel/TARGET_SAM21/sercom_dma.h | 62 + .../TARGET_Atmel/TARGET_SAM21/serial_api.c | 1032 ++ .../hal/TARGET_Atmel/TARGET_SAM21/sleep_api.c | 49 + .../hal/TARGET_Atmel/TARGET_SAM21/spi_api.c | 941 + .../hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c | 165 + .../hal/TARGET_Atmel/common/boards/board.h | 344 + .../hal/TARGET_Atmel/common/utils/interrupt.h | 97 + .../utils/interrupt/interrupt_sam_nvic.c | 40 + .../utils/interrupt/interrupt_sam_nvic.h | 143 + targets/hal/TARGET_Atmel/common/utils/parts.h | 1234 ++ .../common2/services/delay/delay.h | 60 + .../services/delay/sam0/systick_counter.c | 50 + .../services/delay/sam0/systick_counter.h | 68 + targets/hal/TARGET_Atmel/config/conf_board.h | 4 + targets/hal/TARGET_Atmel/config/conf_clocks.h | 145 + targets/hal/TARGET_Atmel/config/conf_dma.h | 6 + targets/hal/TARGET_Atmel/config/conf_extint.h | 6 + targets/hal/TARGET_Atmel/config/conf_spi.h | 9 + .../TARGET_K20XX/PeripheralPins.h | 46 + .../TARGET_Freescale/TARGET_K20XX/PortNames.h | 35 + .../TARGET_K20D50M/PeripheralNames.h | 73 + .../TARGET_K20D50M/PeripheralPins.c | 120 + .../TARGET_K20XX/TARGET_K20D50M/PinNames.h | 256 + .../TARGET_K20XX/TARGET_K20D50M/device.h | 58 + .../TARGET_TEENSY3_1/PeripheralNames.h | 86 + .../TARGET_TEENSY3_1/PeripheralPins.c | 137 + .../TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h | 310 + .../TARGET_K20XX/TARGET_TEENSY3_1/device.h | 58 + .../TARGET_K20XX/analogin_api.c | 78 + .../TARGET_K20XX/analogout_api.c | 84 + .../TARGET_Freescale/TARGET_K20XX/clk_freqs.h | 115 + .../TARGET_Freescale/TARGET_K20XX/gpio_api.c | 56 + .../TARGET_K20XX/gpio_irq_api.c | 225 + .../TARGET_K20XX/gpio_object.h | 56 + .../TARGET_Freescale/TARGET_K20XX/i2c_api.c | 378 + .../TARGET_Freescale/TARGET_K20XX/objects.h | 77 + .../TARGET_Freescale/TARGET_K20XX/pinmap.c | 38 + .../TARGET_Freescale/TARGET_K20XX/port_api.c | 72 + .../TARGET_K20XX/pwmout_api.c | 116 + .../TARGET_Freescale/TARGET_K20XX/rtc_api.c | 91 + .../TARGET_K20XX/serial_api.c | 301 + .../hal/TARGET_Freescale/TARGET_K20XX/sleep.c | 83 + .../TARGET_Freescale/TARGET_K20XX/spi_api.c | 143 + .../TARGET_Freescale/TARGET_K20XX/us_ticker.c | 159 + .../TARGET_KLXX/PeripheralPins.h | 49 + .../TARGET_Freescale/TARGET_KLXX/PortNames.h | 34 + .../TARGET_KL05Z/PeripheralNames.h | 85 + .../TARGET_KLXX/TARGET_KL05Z/PeripheralPins.c | 123 + .../TARGET_KLXX/TARGET_KL05Z/PinNames.h | 136 + .../TARGET_KLXX/TARGET_KL05Z/device.h | 58 + .../TARGET_KLXX/TARGET_KL05Z/gpio_irq_api.c | 180 + .../TARGET_KLXX/TARGET_KL05Z/mbed_overrides.c | 32 + .../TARGET_KLXX/TARGET_KL05Z/serial_api.c | 295 + .../TARGET_KLXX/TARGET_KL05Z/spi_api.c | 155 + .../TARGET_KL25Z/PeripheralNames.h | 119 + .../TARGET_KLXX/TARGET_KL25Z/PeripheralPins.c | 197 + .../TARGET_KLXX/TARGET_KL25Z/PinNames.h | 254 + .../TARGET_KLXX/TARGET_KL25Z/device.h | 58 + .../TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c | 170 + .../TARGET_KLXX/TARGET_KL25Z/mbed_overrides.c | 32 + .../TARGET_KLXX/TARGET_KL25Z/serial_api.c | 305 + .../TARGET_KLXX/TARGET_KL25Z/spi_api.c | 134 + .../TARGET_KL26Z/PeripheralNames.h | 95 + .../TARGET_KLXX/TARGET_KL26Z/PeripheralPins.c | 197 + .../TARGET_KLXX/TARGET_KL26Z/PinNames.h | 254 + .../TARGET_KLXX/TARGET_KL26Z/device.h | 58 + .../TARGET_KLXX/TARGET_KL26Z/gpio_irq_api.c | 170 + .../TARGET_KLXX/TARGET_KL26Z/mbed_overrides.c | 32 + .../TARGET_KLXX/TARGET_KL26Z/serial_api.c | 305 + .../TARGET_KLXX/TARGET_KL26Z/spi_api.c | 226 + .../TARGET_KL43Z/PeripheralNames.h | 94 + .../TARGET_KLXX/TARGET_KL43Z/PeripheralPins.c | 184 + .../TARGET_KLXX/TARGET_KL43Z/PinNames.h | 258 + .../TARGET_KLXX/TARGET_KL43Z/device.h | 58 + .../TARGET_KLXX/TARGET_KL43Z/gpio_irq_api.c | 191 + .../TARGET_KLXX/TARGET_KL43Z/mbed_overrides.c | 32 + .../TARGET_KLXX/TARGET_KL43Z/serial_api.c | 316 + .../TARGET_KLXX/TARGET_KL43Z/spi_api.c | 210 + .../TARGET_KL46Z/PeripheralNames.h | 94 + .../TARGET_KLXX/TARGET_KL46Z/PeripheralPins.c | 209 + .../TARGET_KLXX/TARGET_KL46Z/PinNames.h | 258 + .../TARGET_KLXX/TARGET_KL46Z/device.h | 58 + .../TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c | 191 + .../TARGET_KLXX/TARGET_KL46Z/mbed_overrides.c | 32 + .../TARGET_KLXX/TARGET_KL46Z/serial_api.c | 305 + .../TARGET_KLXX/TARGET_KL46Z/spi_api.c | 226 + .../TARGET_KLXX/analogin_api.c | 87 + .../TARGET_KLXX/analogout_api.c | 80 + .../TARGET_Freescale/TARGET_KLXX/clk_freqs.h | 144 + .../TARGET_Freescale/TARGET_KLXX/gpio_api.c | 60 + .../TARGET_KLXX/gpio_object.h | 56 + .../TARGET_Freescale/TARGET_KLXX/i2c_api.c | 383 + .../TARGET_Freescale/TARGET_KLXX/objects.h | 83 + .../hal/TARGET_Freescale/TARGET_KLXX/pinmap.c | 39 + .../TARGET_Freescale/TARGET_KLXX/port_api.c | 70 + .../TARGET_Freescale/TARGET_KLXX/pwmout_api.c | 125 + .../TARGET_Freescale/TARGET_KLXX/rtc_api.c | 96 + .../hal/TARGET_Freescale/TARGET_KLXX/sleep.c | 70 + .../TARGET_Freescale/TARGET_KLXX/us_ticker.c | 204 + .../TARGET_KPSDK_MCUS/PeripheralPins.h | 49 + .../TARGET_KPSDK_MCUS/PortNames.h | 35 + .../MK22F51212/fsl_clock_K22F51212.c | 477 + .../MK22F51212/fsl_clock_K22F51212.h | 1033 ++ .../MK22F51212/fsl_sim_hal_K22F51212.c | 1187 ++ .../MK22F51212/fsl_sim_hal_K22F51212.h | 839 + .../TARGET_K22F/PeripheralNames.h | 125 + .../TARGET_K22F/PeripheralPins.c | 179 + .../TARGET_KPSDK_MCUS/TARGET_K22F/PinNames.h | 259 + .../TARGET_KPSDK_MCUS/TARGET_K22F/device.h | 58 + .../device/MK22F51212/MK22F51212.h | 10137 +++++++++++ .../device/MK22F51212/MK22F51212_adc.h | 2339 +++ .../device/MK22F51212/MK22F51212_aips.h | 13604 +++++++++++++++ .../device/MK22F51212/MK22F51212_cmp.h | 940 + .../device/MK22F51212/MK22F51212_crc.h | 1406 ++ .../device/MK22F51212/MK22F51212_dac.h | 837 + .../device/MK22F51212/MK22F51212_dma.h | 5785 +++++++ .../device/MK22F51212/MK22F51212_dmamux.h | 237 + .../device/MK22F51212/MK22F51212_ewm.h | 504 + .../device/MK22F51212/MK22F51212_fb.h | 904 + .../device/MK22F51212/MK22F51212_fmc.h | 1979 +++ .../device/MK22F51212/MK22F51212_ftfa.h | 3194 ++++ .../device/MK22F51212/MK22F51212_ftm.h | 5936 +++++++ .../device/MK22F51212/MK22F51212_gpio.h | 487 + .../device/MK22F51212/MK22F51212_i2c.h | 1724 ++ .../device/MK22F51212/MK22F51212_i2s.h | 3270 ++++ .../device/MK22F51212/MK22F51212_llwu.h | 1950 +++ .../device/MK22F51212/MK22F51212_lptmr.h | 614 + .../device/MK22F51212/MK22F51212_lpuart.h | 2519 +++ .../device/MK22F51212/MK22F51212_mcg.h | 1779 ++ .../device/MK22F51212/MK22F51212_mcm.h | 713 + .../device/MK22F51212/MK22F51212_nv.h | 869 + .../device/MK22F51212/MK22F51212_osc.h | 378 + .../device/MK22F51212/MK22F51212_pdb.h | 1326 ++ .../device/MK22F51212/MK22F51212_pit.h | 516 + .../device/MK22F51212/MK22F51212_pmc.h | 572 + .../device/MK22F51212/MK22F51212_port.h | 892 + .../device/MK22F51212/MK22F51212_rcm.h | 1154 ++ .../device/MK22F51212/MK22F51212_rfsys.h | 239 + .../device/MK22F51212/MK22F51212_rfvbat.h | 239 + .../device/MK22F51212/MK22F51212_rng.h | 587 + .../device/MK22F51212/MK22F51212_rtc.h | 1659 ++ .../device/MK22F51212/MK22F51212_sim.h | 4023 +++++ .../device/MK22F51212/MK22F51212_smc.h | 597 + .../device/MK22F51212/MK22F51212_spi.h | 2239 +++ .../device/MK22F51212/MK22F51212_uart.h | 4876 ++++++ .../device/MK22F51212/MK22F51212_usb.h | 3804 ++++ .../device/MK22F51212/MK22F51212_vref.h | 384 + .../device/MK22F51212/MK22F51212_wdog.h | 1153 ++ .../device/MK22F51212/fsl_bitaccess.h | 526 + .../TARGET_K22F/device/fsl_device_registers.h | 1526 ++ .../TARGET_K22F/mbed_overrides.c | 33 + .../common/phyksz8081/fsl_phy_driver.c | 267 + .../common/phyksz8081/fsl_phy_driver.h | 195 + .../drivers/clock/fsl_clock_manager.c | 299 + .../drivers/clock/fsl_clock_manager.h | 429 + .../drivers/enet/fsl_enet_driver.h | 952 + .../drivers/enet/fsl_enet_rtcs_adapter.h | 513 + .../drivers/enet/src/fsl_enet_irq.c | 89 + .../TARGET_KPSDK_CODE/drivers/enet/subdir.mk | 4 + .../interrupt/fsl_interrupt_features.h | 126 + .../drivers/interrupt/fsl_interrupt_manager.h | 142 + .../drivers/pit/common/fsl_pit_common.c | 47 + .../drivers/pit/common/fsl_pit_common.h | 49 + .../drivers/pit/fsl_pit_driver.h | 251 + .../drivers/pit/src/fsl_pit_driver.c | 264 + .../drivers/pit/src/fsl_pit_irq.c | 154 + .../hal/adc/fsl_adc_features.h | 220 + .../TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c | 152 + .../TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h | 906 + .../hal/can/fsl_flexcan_features.h | 119 + .../hal/can/fsl_flexcan_hal.c | 1845 ++ .../hal/can/fsl_flexcan_hal.h | 837 + .../hal/dac/fsl_dac_features.h | 100 + .../TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c | 105 + .../TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h | 488 + .../hal/dmamux/fsl_dmamux_features.h | 114 + .../hal/dmamux/fsl_dmamux_hal.c | 56 + .../hal/dmamux/fsl_dmamux_hal.h | 136 + .../hal/dspi/fsl_dspi_features.h | 247 + .../TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c | 604 + .../TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h | 900 + .../hal/edma/fsl_edma_features.h | 135 + .../TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c | 633 + .../TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h | 1418 ++ .../hal/enet/fsl_enet_features.h | 56 + .../TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c | 557 + .../TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h | 1420 ++ .../hal/flextimer/fsl_ftm_features.h | 156 + .../hal/flextimer/fsl_ftm_hal.c | 186 + .../hal/flextimer/fsl_ftm_hal.h | 1433 ++ .../hal/gpio/fsl_gpio_features.h | 188 + .../TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.c | 77 + .../TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.h | 406 + .../hal/i2c/fsl_i2c_features.h | 283 + .../TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c | 291 + .../TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h | 702 + .../hal/llwu/fsl_llwu_features.h | 153 + .../TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c | 616 + .../TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h | 248 + .../hal/lptmr/fsl_lptmr_features.h | 86 + .../hal/lptmr/fsl_lptmr_hal.c | 68 + .../hal/lptmr/fsl_lptmr_hal.h | 413 + .../hal/lpuart/fsl_lpuart_features.h | 220 + .../hal/lpuart/fsl_lpuart_hal.c | 782 + .../hal/lpuart/fsl_lpuart_hal.h | 1134 ++ .../hal/mcg/fsl_mcg_features.h | 705 + .../TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c | 432 + .../TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h | 2184 +++ .../hal/mcg/fsl_mcg_hal_modes.c | 2501 +++ .../hal/mcg/fsl_mcg_hal_modes.h | 526 + .../hal/mpu/fsl_mpu_features.h | 146 + .../TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c | 71 + .../TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h | 1545 ++ .../hal/osc/fsl_osc_features.h | 166 + .../TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c | 192 + .../TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h | 177 + .../hal/pdb/fsl_pdb_features.h | 87 + .../TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c | 232 + .../TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h | 631 + .../hal/pit/fsl_pit_features.h | 127 + .../TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c | 63 + .../TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h | 336 + .../hal/pmc/fsl_pmc_features.h | 109 + .../TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c | 68 + .../TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h | 321 + .../hal/port/fsl_port_features.h | 333 + .../TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c | 68 + .../TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h | 450 + .../hal/rcm/fsl_rcm_features.h | 109 + .../TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c | 109 + .../TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h | 199 + .../hal/rtc/fsl_rtc_features.h | 144 + .../TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c | 381 + .../TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h | 1976 +++ .../hal/sai/fsl_sai_features.h | 168 + .../TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c | 835 + .../TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h | 1423 ++ .../hal/sdhc/fsl_sdhc_features.h | 84 + .../TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c | 167 + .../TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h | 1236 ++ .../hal/sim/fsl_sim_features.h | 4222 +++++ .../TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c | 1468 ++ .../TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h | 1620 ++ .../hal/smc/fsl_smc_features.h | 245 + .../TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c | 671 + .../TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h | 475 + .../hal/uart/fsl_uart_features.h | 1218 ++ .../TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c | 961 + .../TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h | 1333 ++ .../hal/wdog/fsl_wdog_features.h | 87 + .../TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c | 75 + .../TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h | 609 + .../TARGET_KPSDK_CODE/mbed KSDK readme.txt | 15 + .../utilities/fsl_misc_utilities.h | 60 + .../utilities/fsl_os_abstraction.h | 572 + .../utilities/fsl_os_abstraction_mbed.h | 38 + .../utilities/src/fsl_misc_utilities.c | 68 + .../utilities/src/fsl_os_abstraction_mbed.c | 35 + .../TARGET_KPSDK_CODE/utilities/sw_timer.h | 191 + .../MK64F12/fsl_clock_K64F12.c | 592 + .../MK64F12/fsl_clock_K64F12.h | 1248 ++ .../MK64F12/fsl_sim_hal_K64F12.c | 1410 ++ .../MK64F12/fsl_sim_hal_K64F12.h | 1009 ++ .../TARGET_FRDM/PeripheralNames.h | 131 + .../TARGET_FRDM/PeripheralPins.c | 202 + .../TARGET_MCU_K64F/TARGET_FRDM/PinNames.h | 258 + .../TARGET_MCU_K64F/TARGET_FRDM/crc.c | 234 + .../TARGET_MCU_K64F/TARGET_FRDM/crc.h | 77 + .../TARGET_MCU_K64F/TARGET_FRDM/device.h | 58 + .../TARGET_FRDM/mbed_overrides.c | 72 + .../TARGET_MTS_GAMBIT/PeripheralNames.h | 133 + .../TARGET_MTS_GAMBIT/PeripheralPins.c | 112 + .../TARGET_MTS_GAMBIT/PinNames.h | 268 + .../TARGET_MTS_GAMBIT/device.h | 58 + .../TARGET_MTS_GAMBIT/mbed_overrides.c | 23 + .../device/MK64F12/fsl_bitaccess.h | 529 + .../device/device/MK64F12/MK64F12.h | 14420 ++++++++++++++++ .../device/device/MK64F12/MK64F12_adc.h | 2342 +++ .../device/device/MK64F12/MK64F12_aips.h | 12467 +++++++++++++ .../device/device/MK64F12/MK64F12_axbs.h | 1030 ++ .../device/device/MK64F12/MK64F12_can.h | 3579 ++++ .../device/device/MK64F12/MK64F12_cau.h | 5229 ++++++ .../device/device/MK64F12/MK64F12_cmp.h | 942 + .../device/device/MK64F12/MK64F12_cmt.h | 1120 ++ .../device/device/MK64F12/MK64F12_crc.h | 1409 ++ .../device/device/MK64F12/MK64F12_dac.h | 818 + .../device/device/MK64F12/MK64F12_dma.h | 5365 ++++++ .../device/device/MK64F12/MK64F12_dmamux.h | 241 + .../device/device/MK64F12/MK64F12_enet.h | 7497 ++++++++ .../device/device/MK64F12/MK64F12_ewm.h | 440 + .../device/device/MK64F12/MK64F12_fb.h | 907 + .../device/device/MK64F12/MK64F12_fmc.h | 1982 +++ .../device/device/MK64F12/MK64F12_ftfe.h | 2344 +++ .../device/device/MK64F12/MK64F12_ftm.h | 5910 +++++++ .../device/device/MK64F12/MK64F12_gpio.h | 490 + .../device/device/MK64F12/MK64F12_i2c.h | 1728 ++ .../device/device/MK64F12/MK64F12_i2s.h | 3098 ++++ .../device/device/MK64F12/MK64F12_llwu.h | 2052 +++ .../device/device/MK64F12/MK64F12_lptmr.h | 617 + .../device/device/MK64F12/MK64F12_mcg.h | 1782 ++ .../device/device/MK64F12/MK64F12_mcm.h | 1089 ++ .../device/device/MK64F12/MK64F12_mpu.h | 1741 ++ .../device/device/MK64F12/MK64F12_nv.h | 929 + .../device/device/MK64F12/MK64F12_osc.h | 312 + .../device/device/MK64F12/MK64F12_pdb.h | 1329 ++ .../device/device/MK64F12/MK64F12_pit.h | 519 + .../device/device/MK64F12/MK64F12_pmc.h | 575 + .../device/device/MK64F12/MK64F12_port.h | 895 + .../device/device/MK64F12/MK64F12_rcm.h | 722 + .../device/device/MK64F12/MK64F12_rfsys.h | 242 + .../device/device/MK64F12/MK64F12_rfvbat.h | 242 + .../device/device/MK64F12/MK64F12_rng.h | 590 + .../device/device/MK64F12/MK64F12_rtc.h | 1662 ++ .../device/device/MK64F12/MK64F12_sdhc.h | 5200 ++++++ .../device/device/MK64F12/MK64F12_sim.h | 4084 +++++ .../device/device/MK64F12/MK64F12_smc.h | 566 + .../device/device/MK64F12/MK64F12_spi.h | 2243 +++ .../device/device/MK64F12/MK64F12_uart.h | 4474 +++++ .../device/device/MK64F12/MK64F12_usb.h | 3828 ++++ .../device/device/MK64F12/MK64F12_usbdcd.h | 938 + .../device/device/MK64F12/MK64F12_vref.h | 387 + .../device/device/MK64F12/MK64F12_wdog.h | 1156 ++ .../device/device/fsl_device_registers.h | 1526 ++ .../TARGET_KPSDK_MCUS/analogin_api.c | 79 + .../TARGET_KPSDK_MCUS/analogout_api.c | 83 + .../TARGET_KPSDK_MCUS/gpio_api.c | 62 + .../TARGET_KPSDK_MCUS/gpio_irq_api.c | 215 + .../TARGET_KPSDK_MCUS/gpio_object.h | 57 + .../TARGET_KPSDK_MCUS/i2c_api.c | 328 + .../TARGET_KPSDK_MCUS/objects.h | 69 + .../TARGET_KPSDK_MCUS/pinmap.c | 51 + .../TARGET_KPSDK_MCUS/port_api.c | 77 + .../TARGET_KPSDK_MCUS/pwmout_api.c | 135 + .../TARGET_KPSDK_MCUS/rtc_api.c | 60 + .../TARGET_KPSDK_MCUS/serial_api.c | 233 + .../TARGET_KPSDK_MCUS/sleep.c | 49 + .../TARGET_KPSDK_MCUS/spi_api.c | 133 + .../TARGET_KPSDK_MCUS/us_ticker.c | 82 + .../TARGET_MAX32600/.serial_api.c.swp | Bin 0 -> 16384 bytes .../TARGET_MAX32600/PeripheralPins.c | 272 + .../TARGET_MAX32600/PeripheralPins.h | 65 + .../TARGET_Maxim/TARGET_MAX32600/PortNames.h | 55 + .../TARGET_MAX32600MBED/PeripheralNames.h | 86 + .../TARGET_MAX32600MBED/PinNames.h | 267 + .../TARGET_MAX32600MBED/low_level_init.c | 88 + .../TARGET_MAX32600/analogin_api.c | 147 + .../TARGET_MAX32600/analogout_api.c | 212 + .../hal/TARGET_Maxim/TARGET_MAX32600/device.h | 74 + .../TARGET_Maxim/TARGET_MAX32600/gpio_api.c | 94 + .../TARGET_MAX32600/gpio_irq_api.c | 167 + .../TARGET_MAX32600/gpio_object.h | 71 + .../TARGET_Maxim/TARGET_MAX32600/i2c_api.c | 405 + .../TARGET_Maxim/TARGET_MAX32600/objects.h | 118 + .../hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c | 105 + .../TARGET_Maxim/TARGET_MAX32600/port_api.c | 97 + .../TARGET_Maxim/TARGET_MAX32600/pwmout_api.c | 234 + .../TARGET_Maxim/TARGET_MAX32600/rtc_api.c | 249 + .../TARGET_Maxim/TARGET_MAX32600/serial_api.c | 355 + .../hal/TARGET_Maxim/TARGET_MAX32600/sleep.c | 123 + .../TARGET_Maxim/TARGET_MAX32600/spi_api.c | 190 + .../TARGET_Maxim/TARGET_MAX32600/us_ticker.c | 263 + .../TARGET_MAX32610/PeripheralPins.c | 190 + .../TARGET_MAX32610/PeripheralPins.h | 65 + .../TARGET_Maxim/TARGET_MAX32610/PortNames.h | 50 + .../TARGET_MAXWSNENV/PeripheralNames.h | 86 + .../TARGET_MAXWSNENV/PinNames.h | 177 + .../TARGET_MAXWSNENV/low_level_init.c | 48 + .../TARGET_MAX32610/analogin_api.c | 147 + .../TARGET_MAX32610/analogout_api.c | 212 + .../hal/TARGET_Maxim/TARGET_MAX32610/device.h | 74 + .../TARGET_Maxim/TARGET_MAX32610/gpio_api.c | 94 + .../TARGET_MAX32610/gpio_irq_api.c | 168 + .../TARGET_MAX32610/gpio_object.h | 71 + .../TARGET_Maxim/TARGET_MAX32610/i2c_api.c | 405 + .../TARGET_Maxim/TARGET_MAX32610/objects.h | 118 + .../hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c | 105 + .../TARGET_Maxim/TARGET_MAX32610/port_api.c | 97 + .../TARGET_Maxim/TARGET_MAX32610/pwmout_api.c | 234 + .../TARGET_Maxim/TARGET_MAX32610/rtc_api.c | 249 + .../TARGET_Maxim/TARGET_MAX32610/serial_api.c | 355 + .../hal/TARGET_Maxim/TARGET_MAX32610/sleep.c | 123 + .../TARGET_Maxim/TARGET_MAX32610/spi_api.c | 186 + .../TARGET_Maxim/TARGET_MAX32610/us_ticker.c | 263 + .../TARGET_MCU_NRF51822/.objects.h.swp | Bin 0 -> 12288 bytes .../components/libraries/crc16/crc16.h | 51 + .../libraries/scheduler/app_scheduler.h | 152 + .../components/libraries/util/app_error.h | 92 + .../components/libraries/util/app_util.h | 234 + .../s110_nrf51822_8.0.0_licence_agreement.txt | 90 + .../s110_nrf51822_8.0.0_softdevice.hex | 5649 ++++++ .../s130_nrf51_1.0.0_licence_agreement.txt | 90 + .../s130_nrf51_1.0.0_softdevice.hex | 6861 ++++++++ .../TARGET_MCU_NRF51822/PeripheralNames.h | 58 + .../TARGET_MCU_NRF51822/PortNames.h | 30 + .../TARGET_ARCH_BLE/PinNames.h | 177 + .../TARGET_ARCH_BLE/device.h | 57 + .../TARGET_DELTA_DFCM_NNN40/PinNames.h | 130 + .../TARGET_DELTA_DFCM_NNN40/device.h | 57 + .../TARGET_DELTA_DFCM_NNN40/mbed_overrides.c | 123 + .../TARGET_DELTA_DFCM_NNN40/rtc_api.c | 71 + .../TARGET_HRM1017/PinNames.h | 153 + .../TARGET_HRM1017/device.h | 57 + .../TARGET_NRF51822_MKIT/PinNames.h | 153 + .../TARGET_NRF51822_MKIT/device.h | 57 + .../TARGET_NRF51822_SBKIT/PinNames.h | 106 + .../TARGET_NRF51822_SBKIT/device.h | 57 + .../TARGET_NRF51822_Y5_MBUG/PinNames.h | 150 + .../TARGET_NRF51822_Y5_MBUG/device.h | 57 + .../TARGET_NRF51_DK/PinNames.h | 178 + .../TARGET_NRF51_DK/device.h | 57 + .../TARGET_NRF51_DONGLE/PinNames.h | 145 + .../TARGET_NRF51_DONGLE/device.h | 57 + .../TARGET_NRF51_MICROBIT/PinNames.h | 198 + .../TARGET_NRF51_MICROBIT/device.h | 57 + .../TARGET_RBLAB_BLENANO/PinNames.h | 174 + .../TARGET_RBLAB_BLENANO/device.h | 57 + .../TARGET_RBLAB_NRF51822/PinNames.h | 193 + .../TARGET_RBLAB_NRF51822/device.h | 57 + .../TARGET_SEEED_TINY_BLE/PinNames.h | 143 + .../TARGET_SEEED_TINY_BLE/device.h | 57 + .../TARGET_WALLBOT_BLE/PinNames.h | 180 + .../TARGET_WALLBOT_BLE/device.h | 57 + .../TARGET_MCU_NRF51822/analogin_api.c | 75 + .../TARGET_MCU_NRF51822/gpio_api.c | 58 + .../TARGET_MCU_NRF51822/gpio_irq_api.c | 127 + .../TARGET_MCU_NRF51822/gpio_object.h | 56 + .../TARGET_MCU_NRF51822/i2c_api.c | 308 + .../TARGET_MCU_NRF51822/objects.h | 86 + .../TARGET_MCU_NRF51822/pinmap.c | 32 + .../TARGET_MCU_NRF51822/port_api.c | 84 + .../TARGET_MCU_NRF51822/pwmout_api.c | 347 + .../TARGET_MCU_NRF51822/serial_api.c | 300 + .../TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c | 32 + .../TARGET_MCU_NRF51822/spi_api.c | 286 + .../TARGET_MCU_NRF51822/twi_config.h | 20 + .../TARGET_MCU_NRF51822/twi_master.c | 303 + .../TARGET_MCU_NRF51822/twi_master.h | 108 + .../TARGET_MCU_NRF51822/us_ticker.c | 272 + .../TARGET_LPC11U6X/PeripheralNames.h | 73 + .../hal/TARGET_NXP/TARGET_LPC11U6X/PinNames.h | 181 + .../TARGET_NXP/TARGET_LPC11U6X/PortNames.h | 32 + .../TARGET_NXP/TARGET_LPC11U6X/analogin_api.c | 136 + .../hal/TARGET_NXP/TARGET_LPC11U6X/device.h | 57 + .../hal/TARGET_NXP/TARGET_LPC11U6X/gpio_api.c | 76 + .../TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c | 143 + .../TARGET_NXP/TARGET_LPC11U6X/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c | 394 + .../hal/TARGET_NXP/TARGET_LPC11U6X/objects.h | 80 + .../hal/TARGET_NXP/TARGET_LPC11U6X/pinmap.c | 45 + .../TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c | 188 + .../hal/TARGET_NXP/TARGET_LPC11U6X/rtc_api.c | 64 + .../TARGET_NXP/TARGET_LPC11U6X/serial_api.c | 462 + .../hal/TARGET_NXP/TARGET_LPC11U6X/sleep.c | 69 + .../hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c | 210 + .../TARGET_NXP/TARGET_LPC11U6X/us_ticker.c | 62 + .../TARGET_LPC11UXX/PeripheralPins.h | 43 + .../TARGET_NXP/TARGET_LPC11UXX/PortNames.h | 31 + .../PeripheralNames.h | 71 + .../PeripheralPins.c | 117 + .../TARGET_APPNEARME_MICRONFCBOARD/PinNames.h | 178 + .../TARGET_APPNEARME_MICRONFCBOARD/device.h | 59 + .../TARGET_ARCH_GPRS/PeripheralNames.h | 87 + .../TARGET_ARCH_GPRS/PeripheralPins.c | 117 + .../TARGET_ARCH_GPRS/PinNames.h | 195 + .../TARGET_LPC11UXX/TARGET_ARCH_GPRS/device.h | 59 + .../TARGET_LPC11U24_301/PeripheralNames.h | 87 + .../TARGET_LPC11U24_301/PeripheralPins.c | 117 + .../TARGET_LPC11U24_301/PinNames.h | 166 + .../TARGET_LPC11U24_301/device.h | 59 + .../TARGET_LPC11U24_401/PeripheralNames.h | 87 + .../TARGET_LPC11U24_401/PeripheralPins.c | 117 + .../TARGET_LPC11U24_401/PinNames.h | 195 + .../TARGET_LPC11U24_401/device.h | 59 + .../TARGET_LPC11U34_421/PeripheralNames.h | 71 + .../TARGET_LPC11U34_421/PeripheralPins.c | 117 + .../TARGET_LPC11U34_421/PinNames.h | 138 + .../TARGET_LPC11U34_421/device.h | 59 + .../TARGET_LPC11U35_401/PeripheralNames.h | 71 + .../TARGET_LPC11U35_401/PeripheralPins.c | 117 + .../TARGET_LPC11U35_401/PinNames.h | 166 + .../TARGET_LPC11U35_401/device.h | 59 + .../TARGET_LPC11U37H_401/PeripheralNames.h | 71 + .../TARGET_LPC11U37H_401/PeripheralPins.c | 117 + .../TARGET_LPC11U37H_401/PinNames.h | 176 + .../TARGET_LPC11U37H_401/device.h | 59 + .../TARGET_LPCCAPPUCCINO/PeripheralNames.h | 71 + .../TARGET_LPCCAPPUCCINO/PeripheralPins.c | 117 + .../TARGET_LPCCAPPUCCINO/PinNames.h | 139 + .../TARGET_LPCCAPPUCCINO/device.h | 59 + .../TARGET_MCU_LPC11U35_501/PeripheralNames.h | 71 + .../TARGET_MCU_LPC11U35_501/PeripheralPins.c | 117 + .../TARGET_LPC11U35_501/PinNames.h | 181 + .../TARGET_LPC11U35_501/device.h | 59 + .../TARGET_LPC11U35_501_IBDAP/PinNames.h | 184 + .../TARGET_LPC11U35_501_IBDAP/device.h | 59 + .../TARGET_LPC11U35_Y5_MBUG/PinNames.h | 140 + .../TARGET_LPC11U35_Y5_MBUG/device.h | 59 + .../TARGET_XADOW_M0/PinNames.h | 184 + .../TARGET_XADOW_M0/device.h | 59 + .../TARGET_OC_MBUINO/PeripheralNames.h | 91 + .../TARGET_OC_MBUINO/PeripheralPins.c | 106 + .../TARGET_OC_MBUINO/PinNames.h | 105 + .../TARGET_LPC11UXX/TARGET_OC_MBUINO/device.h | 59 + .../TARGET_NXP/TARGET_LPC11UXX/analogin_api.c | 114 + .../hal/TARGET_NXP/TARGET_LPC11UXX/gpio_api.c | 64 + .../TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c | 141 + .../TARGET_NXP/TARGET_LPC11UXX/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c | 375 + .../hal/TARGET_NXP/TARGET_LPC11UXX/objects.h | 66 + .../hal/TARGET_NXP/TARGET_LPC11UXX/pinmap.c | 56 + .../hal/TARGET_NXP/TARGET_LPC11UXX/port_api.c | 67 + .../TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c | 157 + .../TARGET_NXP/TARGET_LPC11UXX/serial_api.c | 288 + .../hal/TARGET_NXP/TARGET_LPC11UXX/sleep.c | 79 + .../hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c | 174 + .../TARGET_NXP/TARGET_LPC11UXX/us_ticker.c | 62 + .../TARGET_LPC11XX_11CXX/PeripheralNames.h | 65 + .../TARGET_LPC11XX_11CXX/PortNames.h | 33 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/README.md | 4 + .../TARGET_LPC11CXX/PinNames.h | 219 + .../TARGET_LPC11CXX/can_api.c | 459 + .../TARGET_LPC11CXX/device.h | 59 + .../TARGET_LPC11CXX/reserved_pins.h | 8 + .../TARGET_LPC11XX/PinNames.h | 234 + .../TARGET_LPC11XX/device.h | 59 + .../TARGET_LPC11XX/reserved_pins.h | 8 + .../TARGET_LPC11XX_11CXX/analogin_api.c | 122 + .../TARGET_LPC11XX_11CXX/gpio_api.c | 66 + .../TARGET_LPC11XX_11CXX/gpio_irq_api.c | 216 + .../TARGET_LPC11XX_11CXX/gpio_object.h | 54 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c | 387 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/objects.h | 74 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/pinmap.c | 46 + .../TARGET_LPC11XX_11CXX/port_api.c | 78 + .../TARGET_LPC11XX_11CXX/pwmout_api.c | 188 + .../TARGET_LPC11XX_11CXX/serial_api.c | 301 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/sleep.c | 49 + .../TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c | 210 + .../TARGET_LPC11XX_11CXX/us_ticker.c | 62 + .../TARGET_LPC13XX/PeripheralNames.h | 71 + .../hal/TARGET_NXP/TARGET_LPC13XX/PinNames.h | 156 + .../hal/TARGET_NXP/TARGET_LPC13XX/PortNames.h | 31 + .../TARGET_NXP/TARGET_LPC13XX/analogin_api.c | 125 + .../hal/TARGET_NXP/TARGET_LPC13XX/device.h | 57 + .../hal/TARGET_NXP/TARGET_LPC13XX/gpio_api.c | 58 + .../TARGET_NXP/TARGET_LPC13XX/gpio_irq_api.c | 142 + .../TARGET_NXP/TARGET_LPC13XX/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC13XX/i2c_api.c | 385 + .../hal/TARGET_NXP/TARGET_LPC13XX/objects.h | 70 + .../hal/TARGET_NXP/TARGET_LPC13XX/pinmap.c | 56 + .../hal/TARGET_NXP/TARGET_LPC13XX/port_api.c | 67 + .../TARGET_NXP/TARGET_LPC13XX/pwmout_api.c | 180 + .../TARGET_NXP/TARGET_LPC13XX/serial_api.c | 300 + targets/hal/TARGET_NXP/TARGET_LPC13XX/sleep.c | 43 + .../hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c | 202 + .../hal/TARGET_NXP/TARGET_LPC13XX/us_ticker.c | 62 + .../TARGET_LPC15XX/PeripheralNames.h | 60 + .../hal/TARGET_NXP/TARGET_LPC15XX/PinNames.h | 103 + .../hal/TARGET_NXP/TARGET_LPC15XX/PortNames.h | 32 + .../TARGET_NXP/TARGET_LPC15XX/analogin_api.c | 158 + .../TARGET_NXP/TARGET_LPC15XX/analogout_api.c | 71 + .../hal/TARGET_NXP/TARGET_LPC15XX/can_api.c | 487 + .../hal/TARGET_NXP/TARGET_LPC15XX/device.h | 58 + .../hal/TARGET_NXP/TARGET_LPC15XX/gpio_api.c | 66 + .../TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c | 139 + .../TARGET_NXP/TARGET_LPC15XX/gpio_object.h | 57 + .../hal/TARGET_NXP/TARGET_LPC15XX/i2c_api.c | 217 + .../hal/TARGET_NXP/TARGET_LPC15XX/objects.h | 69 + .../hal/TARGET_NXP/TARGET_LPC15XX/pinmap.c | 41 + .../TARGET_NXP/TARGET_LPC15XX/pwmout_api.c | 170 + .../hal/TARGET_NXP/TARGET_LPC15XX/rtc_api.c | 64 + .../TARGET_NXP/TARGET_LPC15XX/serial_api.c | 316 + .../hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c | 265 + .../hal/TARGET_NXP/TARGET_LPC15XX/us_ticker.c | 73 + .../TARGET_LPC176X/PeripheralNames.h | 111 + .../hal/TARGET_NXP/TARGET_LPC176X/PortNames.h | 34 + .../TARGET_LPC176X/TARGET_ARCH_PRO/PinNames.h | 139 + .../TARGET_LPC176X/TARGET_ARCH_PRO/device.h | 60 + .../TARGET_ARCH_PRO/reserved_pins.h | 8 + .../TARGET_MBED_LPC1768/PinNames.h | 139 + .../TARGET_MBED_LPC1768/device.h | 60 + .../TARGET_MBED_LPC1768/reserved_pins.h | 8 + .../TARGET_UBLOX_C027/C027_api.c | 81 + .../TARGET_UBLOX_C027/C027_api.h | 22 + .../TARGET_UBLOX_C027/PinNames.h | 193 + .../TARGET_LPC176X/TARGET_UBLOX_C027/device.h | 62 + .../TARGET_UBLOX_C027/mbed_overrides.c | 21 + .../TARGET_UBLOX_C027/reserved_pins.h | 8 + .../TARGET_XBED_LPC1768/PinNames.h | 143 + .../TARGET_XBED_LPC1768/device.h | 60 + .../TARGET_XBED_LPC1768/reserved_pins.h | 8 + .../TARGET_NXP/TARGET_LPC176X/analogin_api.c | 125 + .../TARGET_NXP/TARGET_LPC176X/analogout_api.c | 76 + .../hal/TARGET_NXP/TARGET_LPC176X/can_api.c | 450 + .../TARGET_NXP/TARGET_LPC176X/ethernet_api.c | 948 + .../hal/TARGET_NXP/TARGET_LPC176X/gpio_api.c | 53 + .../TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c | 161 + .../TARGET_NXP/TARGET_LPC176X/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC176X/i2c_api.c | 394 + .../hal/TARGET_NXP/TARGET_LPC176X/objects.h | 78 + .../hal/TARGET_NXP/TARGET_LPC176X/pinmap.c | 49 + .../hal/TARGET_NXP/TARGET_LPC176X/port_api.c | 71 + .../TARGET_NXP/TARGET_LPC176X/pwmout_api.c | 171 + .../hal/TARGET_NXP/TARGET_LPC176X/rtc_api.c | 113 + .../TARGET_NXP/TARGET_LPC176X/serial_api.c | 443 + targets/hal/TARGET_NXP/TARGET_LPC176X/sleep.c | 72 + .../hal/TARGET_NXP/TARGET_LPC176X/spi_api.c | 208 + .../hal/TARGET_NXP/TARGET_LPC176X/us_ticker.c | 64 + .../TARGET_LPC23XX/PeripheralNames.h | 110 + .../hal/TARGET_NXP/TARGET_LPC23XX/PinNames.h | 104 + .../hal/TARGET_NXP/TARGET_LPC23XX/PortNames.h | 34 + .../TARGET_NXP/TARGET_LPC23XX/analogin_api.c | 123 + .../TARGET_NXP/TARGET_LPC23XX/analogout_api.c | 75 + .../hal/TARGET_NXP/TARGET_LPC23XX/can_api.c | 303 + .../hal/TARGET_NXP/TARGET_LPC23XX/device.h | 59 + .../TARGET_NXP/TARGET_LPC23XX/ethernet_api.c | 935 + .../hal/TARGET_NXP/TARGET_LPC23XX/gpio_api.c | 53 + .../TARGET_NXP/TARGET_LPC23XX/gpio_irq_api.c | 154 + .../TARGET_NXP/TARGET_LPC23XX/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC23XX/i2c_api.c | 393 + .../hal/TARGET_NXP/TARGET_LPC23XX/objects.h | 78 + .../hal/TARGET_NXP/TARGET_LPC23XX/pinmap.c | 46 + .../hal/TARGET_NXP/TARGET_LPC23XX/port_api.c | 71 + .../TARGET_NXP/TARGET_LPC23XX/pwmout_api.c | 171 + .../hal/TARGET_NXP/TARGET_LPC23XX/rtc_api.c | 117 + .../TARGET_NXP/TARGET_LPC23XX/serial_api.c | 337 + .../hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c | 208 + .../hal/TARGET_NXP/TARGET_LPC23XX/us_ticker.c | 64 + .../TARGET_LPC2460/PeripheralNames.h | 120 + .../hal/TARGET_NXP/TARGET_LPC2460/PinNames.h | 112 + .../hal/TARGET_NXP/TARGET_LPC2460/PortNames.h | 38 + .../TARGET_NXP/TARGET_LPC2460/analogin_api.c | 125 + .../TARGET_NXP/TARGET_LPC2460/analogout_api.c | 75 + .../hal/TARGET_NXP/TARGET_LPC2460/can_api.c | 303 + .../hal/TARGET_NXP/TARGET_LPC2460/device.h | 59 + .../TARGET_NXP/TARGET_LPC2460/ethernet_api.c | 935 + .../hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c | 57 + .../TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c | 154 + .../TARGET_NXP/TARGET_LPC2460/gpio_object.h | 59 + .../hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c | 399 + .../hal/TARGET_NXP/TARGET_LPC2460/objects.h | 78 + .../hal/TARGET_NXP/TARGET_LPC2460/pinmap.c | 46 + .../hal/TARGET_NXP/TARGET_LPC2460/port_api.c | 71 + .../TARGET_NXP/TARGET_LPC2460/pwmout_api.c | 175 + .../hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c | 117 + .../TARGET_NXP/TARGET_LPC2460/serial_api.c | 338 + .../hal/TARGET_NXP/TARGET_LPC2460/spi_api.c | 219 + .../hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c | 64 + .../hal/TARGET_NXP/TARGET_LPC408X/PortNames.h | 35 + .../TARGET_LPC4088/PeripheralNames.h | 119 + .../TARGET_LPC408X/TARGET_LPC4088/PinNames.h | 130 + .../TARGET_LPC4088/analogin_api.c | 125 + .../TARGET_LPC408X/TARGET_LPC4088/can_api.c | 391 + .../TARGET_LPC4088/ethernet_api.c | 1008 ++ .../TARGET_LPC408X/TARGET_LPC4088/i2c_api.c | 416 + .../TARGET_LPC4088/pwmout_api.c | 189 + .../TARGET_LPC4088/serial_api.c | 330 + .../TARGET_LPC408X/TARGET_LPC4088/spi_api.c | 215 + .../TARGET_LPC4088_DM/PeripheralNames.h | 111 + .../TARGET_LPC4088_DM/PinNames.h | 106 + .../TARGET_LPC4088_DM/analogin_api.c | 119 + .../TARGET_LPC4088_DM/can_api.c | 388 + .../TARGET_LPC4088_DM/ethernet_api.c | 964 ++ .../TARGET_LPC4088_DM/i2c_api.c | 402 + .../TARGET_LPC4088_DM/pwmout_api.c | 163 + .../TARGET_LPC4088_DM/serial_api.c | 317 + .../TARGET_LPC4088_DM/spi_api.c | 195 + .../TARGET_NXP/TARGET_LPC408X/analogout_api.c | 75 + .../hal/TARGET_NXP/TARGET_LPC408X/device.h | 59 + .../hal/TARGET_NXP/TARGET_LPC408X/gpio_api.c | 56 + .../TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c | 174 + .../TARGET_NXP/TARGET_LPC408X/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC408X/objects.h | 80 + .../hal/TARGET_NXP/TARGET_LPC408X/pinmap.c | 45 + .../hal/TARGET_NXP/TARGET_LPC408X/port_api.c | 71 + .../hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c | 112 + targets/hal/TARGET_NXP/TARGET_LPC408X/sleep.c | 57 + .../hal/TARGET_NXP/TARGET_LPC408X/us_ticker.c | 64 + .../TARGET_LPC43XX/PeripheralNames.h | 135 + .../hal/TARGET_NXP/TARGET_LPC43XX/PortNames.h | 37 + .../hal/TARGET_NXP/TARGET_LPC43XX/README.txt | 81 + .../TARGET_LPC43XX/TARGET_LPC4330/PinNames.h | 705 + .../TARGET_LPC43XX/TARGET_LPC4330/device.h | 60 + .../TARGET_LPC43XX/TARGET_LPC4337/PinNames.h | 523 + .../TARGET_LPC43XX/TARGET_LPC4337/device.h | 59 + .../TARGET_NXP/TARGET_LPC43XX/analogin_api.c | 134 + .../TARGET_NXP/TARGET_LPC43XX/analogout_api.c | 86 + .../TARGET_NXP/TARGET_LPC43XX/ethernet_api.c | 528 + .../hal/TARGET_NXP/TARGET_LPC43XX/gpio_api.c | 63 + .../TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c | 154 + .../TARGET_NXP/TARGET_LPC43XX/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC43XX/i2c_api.c | 395 + .../hal/TARGET_NXP/TARGET_LPC43XX/objects.h | 79 + .../hal/TARGET_NXP/TARGET_LPC43XX/pinmap.c | 42 + .../hal/TARGET_NXP/TARGET_LPC43XX/port_api.c | 146 + .../TARGET_NXP/TARGET_LPC43XX/pwmout_api.c | 266 + .../hal/TARGET_NXP/TARGET_LPC43XX/rtc_api.c | 128 + .../TARGET_NXP/TARGET_LPC43XX/serial_api.c | 410 + targets/hal/TARGET_NXP/TARGET_LPC43XX/sleep.c | 36 + .../hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c | 214 + .../hal/TARGET_NXP/TARGET_LPC43XX/us_ticker.c | 64 + .../hal/TARGET_NXP/TARGET_LPC81X/PortNames.h | 30 + .../TARGET_LPC810/PeripheralNames.h | 30 + .../TARGET_LPC81X/TARGET_LPC810/PinNames.h | 81 + .../TARGET_LPC812/PeripheralNames.h | 37 + .../TARGET_LPC81X/TARGET_LPC812/PinNames.h | 109 + targets/hal/TARGET_NXP/TARGET_LPC81X/device.h | 58 + .../hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c | 70 + .../TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c | 135 + .../TARGET_NXP/TARGET_LPC81X/gpio_object.h | 56 + .../hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c | 513 + .../hal/TARGET_NXP/TARGET_LPC81X/objects.h | 57 + targets/hal/TARGET_NXP/TARGET_LPC81X/pinmap.c | 51 + .../hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c | 227 + .../hal/TARGET_NXP/TARGET_LPC81X/serial_api.c | 320 + targets/hal/TARGET_NXP/TARGET_LPC81X/sleep.c | 82 + .../hal/TARGET_NXP/TARGET_LPC81X/spi_api.c | 196 + .../hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c | 121 + .../hal/TARGET_NXP/TARGET_LPC82X/PortNames.h | 30 + .../TARGET_LPC824/PeripheralNames.h | 55 + .../TARGET_LPC82X/TARGET_LPC824/PinNames.h | 135 + .../TARGET_LPC82X/TARGET_LPC824/device.h | 58 + .../TARGET_SSCI824/PeripheralNames.h | 55 + .../TARGET_LPC82X/TARGET_SSCI824/PinNames.h | 135 + .../TARGET_LPC82X/TARGET_SSCI824/device.h | 58 + .../TARGET_NXP/TARGET_LPC82X/analogin_api.c | 131 + .../hal/TARGET_NXP/TARGET_LPC82X/gpio_api.c | 72 + .../TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c | 145 + .../TARGET_NXP/TARGET_LPC82X/gpio_object.h | 58 + .../hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c | 598 + .../hal/TARGET_NXP/TARGET_LPC82X/objects.h | 62 + targets/hal/TARGET_NXP/TARGET_LPC82X/pinmap.c | 46 + .../hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c | 172 + .../TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h | 127 + .../hal/TARGET_NXP/TARGET_LPC82X/serial_api.c | 357 + targets/hal/TARGET_NXP/TARGET_LPC82X/sleep.c | 62 + .../hal/TARGET_NXP/TARGET_LPC82X/spi_api.c | 199 + .../hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c | 106 + .../TARGET_RZ_A1H/PeripheralNames.h | 158 + .../TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h | 110 + .../TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h | 34 + .../TARGET_MBED_MBRZA1H/reserved_pins.h | 6 + .../TARGET_RZ_A1H/analogin_api.c | 120 + .../TARGET_RENESAS/TARGET_RZ_A1H/can_api.c | 1009 ++ .../hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h | 68 + .../TARGET_RZ_A1H/ethernet_api.c | 696 + .../TARGET_RZ_A1H/ethernetext_api.h | 20 + .../TARGET_RZ_A1H/gpio_addrdefine.h | 22 + .../TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c | 57 + .../TARGET_RZ_A1H/gpio_irq_api.c | 226 + .../TARGET_RZ_A1H/gpio_object.h | 51 + .../TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c | 751 + .../TARGET_RENESAS/TARGET_RZ_A1H/objects.h | 83 + .../hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c | 53 + .../TARGET_RENESAS/TARGET_RZ_A1H/port_api.c | 65 + .../TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c | 566 + .../TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c | 374 + .../TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c | 636 + .../TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c | 267 + .../TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c | 135 + .../TARGET_STM32F0/PeripheralPins.h | 66 + .../TARGET_DISCO_F051R8/PeripheralNames.h | 81 + .../TARGET_DISCO_F051R8/PeripheralPins.c | 151 + .../TARGET_DISCO_F051R8/PinNames.h | 241 + .../TARGET_DISCO_F051R8/PortNames.h | 48 + .../TARGET_DISCO_F051R8/device.h | 70 + .../TARGET_DISCO_F051R8/objects.h | 109 + .../TARGET_NUCLEO_F030R8/PeripheralNames.h | 76 + .../TARGET_NUCLEO_F030R8/PeripheralPins.c | 151 + .../TARGET_NUCLEO_F030R8/PinNames.h | 188 + .../TARGET_NUCLEO_F030R8/PortNames.h | 48 + .../TARGET_NUCLEO_F030R8/device.h | 70 + .../TARGET_NUCLEO_F030R8/objects.h | 104 + .../TARGET_NUCLEO_F070RB/PeripheralNames.h | 77 + .../TARGET_NUCLEO_F070RB/PeripheralPins.c | 184 + .../TARGET_NUCLEO_F070RB/PinNames.h | 183 + .../TARGET_NUCLEO_F070RB/PortNames.h | 48 + .../TARGET_NUCLEO_F070RB/device.h | 70 + .../TARGET_NUCLEO_F070RB/objects.h | 104 + .../TARGET_NUCLEO_F072RB/PeripheralNames.h | 82 + .../TARGET_NUCLEO_F072RB/PeripheralPins.c | 198 + .../TARGET_NUCLEO_F072RB/PinNames.h | 183 + .../TARGET_NUCLEO_F072RB/PortNames.h | 48 + .../TARGET_NUCLEO_F072RB/device.h | 70 + .../TARGET_NUCLEO_F072RB/objects.h | 109 + .../TARGET_NUCLEO_F091RC/PeripheralNames.h | 86 + .../TARGET_NUCLEO_F091RC/PeripheralPins.c | 220 + .../TARGET_NUCLEO_F091RC/PinNames.h | 184 + .../TARGET_NUCLEO_F091RC/PortNames.h | 48 + .../TARGET_NUCLEO_F091RC/device.h | 70 + .../TARGET_NUCLEO_F091RC/objects.h | 109 + .../TARGET_STM/TARGET_STM32F0/analogin_api.c | 179 + .../TARGET_STM/TARGET_STM32F0/analogout_api.c | 136 + .../hal/TARGET_STM/TARGET_STM32F0/gpio_api.c | 79 + .../TARGET_STM/TARGET_STM32F0/gpio_irq_api.c | 267 + .../TARGET_STM/TARGET_STM32F0/gpio_object.h | 75 + .../hal/TARGET_STM/TARGET_STM32F0/i2c_api.c | 390 + .../TARGET_STM32F0/mbed_overrides.c | 40 + .../hal/TARGET_STM/TARGET_STM32F0/pinmap.c | 139 + .../hal/TARGET_STM/TARGET_STM32F0/port_api.c | 103 + .../TARGET_STM/TARGET_STM32F0/pwmout_api.c | 262 + .../hal/TARGET_STM/TARGET_STM32F0/rtc_api.c | 201 + .../TARGET_STM/TARGET_STM32F0/serial_api.c | 515 + targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c | 107 + .../hal/TARGET_STM/TARGET_STM32F0/spi_api.c | 293 + .../hal/TARGET_STM/TARGET_STM32F0/us_ticker.c | 310 + .../TARGET_STM32F1/PeripheralPins.h | 62 + .../TARGET_DISCO_F100RB/PeripheralNames.h | 74 + .../TARGET_DISCO_F100RB/PeripheralPins.c | 165 + .../TARGET_DISCO_F100RB/PinNames.h | 203 + .../TARGET_DISCO_F100RB/PortNames.h | 48 + .../TARGET_DISCO_F100RB/device.h | 70 + .../TARGET_DISCO_F100RB/objects.h | 105 + .../TARGET_NUCLEO_F103RB/PeripheralNames.h | 74 + .../TARGET_NUCLEO_F103RB/PeripheralPins.c | 165 + .../TARGET_NUCLEO_F103RB/PinNames.h | 180 + .../TARGET_NUCLEO_F103RB/PortNames.h | 48 + .../TARGET_NUCLEO_F103RB/device.h | 70 + .../TARGET_NUCLEO_F103RB/objects.h | 105 + .../TARGET_STM/TARGET_STM32F1/analogin_api.c | 175 + .../hal/TARGET_STM/TARGET_STM32F1/gpio_api.c | 79 + .../TARGET_STM/TARGET_STM32F1/gpio_irq_api.c | 332 + .../TARGET_STM/TARGET_STM32F1/gpio_object.h | 75 + .../hal/TARGET_STM/TARGET_STM32F1/i2c_api.c | 459 + .../TARGET_STM32F1/mbed_overrides.c | 37 + .../hal/TARGET_STM/TARGET_STM32F1/pinmap.c | 211 + .../hal/TARGET_STM/TARGET_STM32F1/port_api.c | 103 + .../TARGET_STM/TARGET_STM32F1/pwmout_api.c | 227 + .../hal/TARGET_STM/TARGET_STM32F1/rtc_api.c | 189 + .../TARGET_STM/TARGET_STM32F1/serial_api.c | 345 + targets/hal/TARGET_STM/TARGET_STM32F1/sleep.c | 62 + .../hal/TARGET_STM/TARGET_STM32F1/spi_api.c | 316 + .../hal/TARGET_STM/TARGET_STM32F1/us_ticker.c | 113 + .../TARGET_STM32F3/PeripheralPins.h | 66 + .../TARGET_DISCO_F303VC/PeripheralNames.h | 88 + .../TARGET_DISCO_F303VC/PeripheralPins.c | 270 + .../TARGET_DISCO_F303VC/PinNames.h | 246 + .../TARGET_DISCO_F303VC/PortNames.h | 49 + .../TARGET_DISCO_F303VC/device.h | 70 + .../TARGET_DISCO_F303VC/objects.h | 114 + .../TARGET_DISCO_F334C8/PeripheralNames.h | 80 + .../TARGET_DISCO_F334C8/PeripheralPins.c | 195 + .../TARGET_DISCO_F334C8/PinNames.h | 181 + .../TARGET_DISCO_F334C8/PortNames.h | 48 + .../TARGET_DISCO_F334C8/device.h | 70 + .../TARGET_DISCO_F334C8/objects.h | 114 + .../TARGET_NUCLEO_F302R8/PeripheralNames.h | 80 + .../TARGET_NUCLEO_F302R8/PeripheralPins.c | 206 + .../TARGET_NUCLEO_F302R8/PinNames.h | 194 + .../TARGET_NUCLEO_F302R8/PortNames.h | 48 + .../TARGET_NUCLEO_F302R8/device.h | 70 + .../TARGET_NUCLEO_F302R8/objects.h | 114 + .../TARGET_NUCLEO_F303RE/PeripheralNames.h | 89 + .../TARGET_NUCLEO_F303RE/PeripheralPins.c | 257 + .../TARGET_NUCLEO_F303RE/PinNames.h | 194 + .../TARGET_NUCLEO_F303RE/PortNames.h | 49 + .../TARGET_NUCLEO_F303RE/device.h | 70 + .../TARGET_NUCLEO_F303RE/objects.h | 114 + .../TARGET_NUCLEO_F334R8/PeripheralNames.h | 80 + .../TARGET_NUCLEO_F334R8/PeripheralPins.c | 212 + .../TARGET_NUCLEO_F334R8/PinNames.h | 194 + .../TARGET_NUCLEO_F334R8/PortNames.h | 49 + .../TARGET_NUCLEO_F334R8/device.h | 70 + .../TARGET_NUCLEO_F334R8/objects.h | 114 + .../TARGET_STM/TARGET_STM32F3/analogin_api.c | 222 + .../TARGET_STM/TARGET_STM32F3/analogout_api.c | 182 + .../hal/TARGET_STM/TARGET_STM32F3/gpio_api.c | 79 + .../TARGET_STM/TARGET_STM32F3/gpio_irq_api.c | 332 + .../TARGET_STM/TARGET_STM32F3/gpio_object.h | 76 + .../hal/TARGET_STM/TARGET_STM32F3/i2c_api.c | 450 + .../TARGET_STM32F3/mbed_overrides.c | 37 + .../hal/TARGET_STM/TARGET_STM32F3/pinmap.c | 145 + .../hal/TARGET_STM/TARGET_STM32F3/port_api.c | 103 + .../TARGET_STM/TARGET_STM32F3/pwmout_api.c | 198 + .../hal/TARGET_STM/TARGET_STM32F3/rtc_api.c | 201 + .../TARGET_STM/TARGET_STM32F3/serial_api.c | 408 + targets/hal/TARGET_STM/TARGET_STM32F3/sleep.c | 61 + .../hal/TARGET_STM/TARGET_STM32F3/spi_api.c | 380 + .../hal/TARGET_STM/TARGET_STM32F3/us_ticker.c | 70 + .../TARGET_STM32F3XX/PeripheralNames.h | 79 + .../TARGET_STM/TARGET_STM32F3XX/PinNames.h | 180 + .../TARGET_STM/TARGET_STM32F3XX/PortNames.h | 49 + .../TARGET_STM32F3XX/analogin_api.c | 191 + .../TARGET_STM32F3XX/analogout_api.c | 110 + .../hal/TARGET_STM/TARGET_STM32F3XX/device.h | 71 + .../TARGET_STM/TARGET_STM32F3XX/gpio_api.c | 74 + .../TARGET_STM32F3XX/gpio_irq_api.c | 255 + .../TARGET_STM/TARGET_STM32F3XX/gpio_object.h | 73 + .../hal/TARGET_STM/TARGET_STM32F3XX/i2c_api.c | 354 + .../TARGET_STM32F3XX/mbed_overrides.c | 35 + .../hal/TARGET_STM/TARGET_STM32F3XX/objects.h | 102 + .../hal/TARGET_STM/TARGET_STM32F3XX/pinmap.c | 135 + .../TARGET_STM/TARGET_STM32F3XX/port_api.c | 97 + .../TARGET_STM/TARGET_STM32F3XX/pwmout_api.c | 274 + .../hal/TARGET_STM/TARGET_STM32F3XX/rtc_api.c | 138 + .../TARGET_STM/TARGET_STM32F3XX/serial_api.c | 312 + .../hal/TARGET_STM/TARGET_STM32F3XX/sleep.c | 55 + .../hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c | 273 + .../TARGET_STM/TARGET_STM32F3XX/us_ticker.c | 81 + .../TARGET_STM32F4/PeripheralPins.h | 66 + .../TARGET_ARCH_MAX/PeripheralNames.h | 91 + .../TARGET_ARCH_MAX/PeripheralPins.c | 204 + .../TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h | 286 + .../TARGET_ARCH_MAX/PortNames.h | 52 + .../TARGET_STM32F4/TARGET_ARCH_MAX/device.h | 70 + .../TARGET_STM32F4/TARGET_ARCH_MAX/objects.h | 113 + .../TARGET_DISCO_F401VC/PeripheralNames.h | 81 + .../TARGET_DISCO_F401VC/PeripheralPins.c | 190 + .../TARGET_DISCO_F401VC/PinNames.h | 176 + .../TARGET_DISCO_F401VC/PortNames.h | 49 + .../TARGET_DISCO_F401VC/device.h | 70 + .../TARGET_DISCO_F401VC/objects.h | 108 + .../TARGET_DISCO_F407VG/PeripheralNames.h | 91 + .../TARGET_DISCO_F407VG/PeripheralPins.c | 262 + .../TARGET_DISCO_F407VG/PinNames.h | 261 + .../TARGET_DISCO_F407VG/PortNames.h | 52 + .../TARGET_DISCO_F407VG/device.h | 70 + .../TARGET_DISCO_F407VG/objects.h | 113 + .../TARGET_DISCO_F429ZI/PeripheralNames.h | 98 + .../TARGET_DISCO_F429ZI/PeripheralPins.c | 285 + .../TARGET_DISCO_F429ZI/PinNames.h | 317 + .../TARGET_DISCO_F429ZI/PortNames.h | 54 + .../TARGET_DISCO_F429ZI/device.h | 70 + .../TARGET_DISCO_F429ZI/objects.h | 113 + .../PeripheralNames.h | 82 + .../PeripheralPins.c | 205 + .../TARGET_MTS_DRAGONFLY_F411RE/PinNames.h | 221 + .../TARGET_MTS_DRAGONFLY_F411RE/PortNames.h | 49 + .../TARGET_MTS_DRAGONFLY_F411RE/device.h | 70 + .../TARGET_MTS_DRAGONFLY_F411RE/objects.h | 108 + .../TARGET_MTS_MDOT_F405RG/PeripheralNames.h | 93 + .../TARGET_MTS_MDOT_F405RG/PeripheralPins.c | 215 + .../TARGET_MTS_MDOT_F405RG/PinNames.h | 160 + .../TARGET_MTS_MDOT_F405RG/PortNames.h | 52 + .../TARGET_MTS_MDOT_F405RG/device.h | 70 + .../TARGET_MTS_MDOT_F405RG/objects.h | 113 + .../TARGET_MTS_MDOT_F411RE/PeripheralNames.h | 82 + .../TARGET_MTS_MDOT_F411RE/PeripheralPins.c | 205 + .../TARGET_MTS_MDOT_F411RE/PinNames.h | 218 + .../TARGET_MTS_MDOT_F411RE/PortNames.h | 49 + .../TARGET_MTS_MDOT_F411RE/device.h | 70 + .../TARGET_MTS_MDOT_F411RE/objects.h | 108 + .../TARGET_NUCLEO_F401RE/PeripheralNames.h | 81 + .../TARGET_NUCLEO_F401RE/PeripheralPins.c | 190 + .../TARGET_NUCLEO_F401RE/PinNames.h | 186 + .../TARGET_NUCLEO_F401RE/PortNames.h | 49 + .../TARGET_NUCLEO_F401RE/device.h | 70 + .../TARGET_NUCLEO_F401RE/objects.h | 108 + .../TARGET_NUCLEO_F411RE/PeripheralNames.h | 82 + .../TARGET_NUCLEO_F411RE/PeripheralPins.c | 205 + .../TARGET_NUCLEO_F411RE/PinNames.h | 185 + .../TARGET_NUCLEO_F411RE/PortNames.h | 49 + .../TARGET_NUCLEO_F411RE/device.h | 70 + .../TARGET_NUCLEO_F411RE/objects.h | 108 + .../TARGET_NUCLEO_F446RE/PeripheralNames.h | 91 + .../TARGET_NUCLEO_F446RE/PeripheralPins.c | 234 + .../TARGET_NUCLEO_F446RE/PinNames.h | 185 + .../TARGET_NUCLEO_F446RE/PortNames.h | 51 + .../TARGET_NUCLEO_F446RE/device.h | 70 + .../TARGET_NUCLEO_F446RE/objects.h | 113 + .../TARGET_UBLOX_C029/PeripheralNames.h | 97 + .../TARGET_UBLOX_C029/PeripheralPins.c | 167 + .../TARGET_UBLOX_C029/PinNames.h | 212 + .../TARGET_UBLOX_C029/PortNames.h | 54 + .../TARGET_STM32F4/TARGET_UBLOX_C029/device.h | 70 + .../TARGET_UBLOX_C029/objects.h | 113 + .../TARGET_STM/TARGET_STM32F4/analogin_api.c | 174 + .../TARGET_STM/TARGET_STM32F4/analogout_api.c | 158 + .../hal/TARGET_STM/TARGET_STM32F4/gpio_api.c | 76 + .../TARGET_STM/TARGET_STM32F4/gpio_irq_api.c | 332 + .../TARGET_STM/TARGET_STM32F4/gpio_object.h | 74 + .../hal/TARGET_STM/TARGET_STM32F4/i2c_api.c | 495 + .../TARGET_STM32F4/mbed_overrides.c | 37 + .../hal/TARGET_STM/TARGET_STM32F4/pinmap.c | 181 + .../hal/TARGET_STM/TARGET_STM32F4/port_api.c | 103 + .../TARGET_STM/TARGET_STM32F4/pwmout_api.c | 276 + .../hal/TARGET_STM/TARGET_STM32F4/rtc_api.c | 203 + .../TARGET_STM/TARGET_STM32F4/serial_api.c | 471 + targets/hal/TARGET_STM/TARGET_STM32F4/sleep.c | 61 + .../hal/TARGET_STM/TARGET_STM32F4/spi_api.c | 387 + .../hal/TARGET_STM/TARGET_STM32F4/us_ticker.c | 69 + .../TARGET_STM32F4XX/PeripheralNames.h | 88 + .../TARGET_STM/TARGET_STM32F4XX/PinNames.h | 69 + .../TARGET_STM/TARGET_STM32F4XX/PortNames.h | 38 + .../TARGET_STM32F4XX/analogin_api.c | 96 + .../hal/TARGET_STM/TARGET_STM32F4XX/device.h | 48 + .../TARGET_STM/TARGET_STM32F4XX/gpio_api.c | 61 + .../TARGET_STM/TARGET_STM32F4XX/gpio_object.h | 57 + .../hal/TARGET_STM/TARGET_STM32F4XX/i2c_api.c | 294 + .../hal/TARGET_STM/TARGET_STM32F4XX/objects.h | 81 + .../hal/TARGET_STM/TARGET_STM32F4XX/pinmap.c | 74 + .../TARGET_STM/TARGET_STM32F4XX/port_api.c | 83 + .../hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c | 221 + .../TARGET_STM/TARGET_STM32F4XX/us_ticker.c | 63 + .../TARGET_STM32F7/PeripheralPins.h | 66 + .../TARGET_DISCO_F746NG/PeripheralNames.h | 99 + .../TARGET_DISCO_F746NG/PeripheralPins.c | 151 + .../TARGET_DISCO_F746NG/PinNames.h | 317 + .../TARGET_DISCO_F746NG/PortNames.h | 54 + .../TARGET_DISCO_F746NG/device.h | 70 + .../TARGET_DISCO_F746NG/objects.h | 114 + .../TARGET_STM/TARGET_STM32F7/analogin_api.c | 214 + .../TARGET_STM/TARGET_STM32F7/analogout_api.c | 158 + .../hal/TARGET_STM/TARGET_STM32F7/gpio_api.c | 76 + .../TARGET_STM/TARGET_STM32F7/gpio_irq_api.c | 332 + .../TARGET_STM/TARGET_STM32F7/gpio_object.h | 75 + .../hal/TARGET_STM/TARGET_STM32F7/i2c_api.c | 438 + .../TARGET_STM32F7/mbed_overrides.c | 39 + .../hal/TARGET_STM/TARGET_STM32F7/pinmap.c | 181 + .../hal/TARGET_STM/TARGET_STM32F7/port_api.c | 103 + .../TARGET_STM/TARGET_STM32F7/pwmout_api.c | 222 + .../hal/TARGET_STM/TARGET_STM32F7/rtc_api.c | 203 + .../TARGET_STM/TARGET_STM32F7/serial_api.c | 474 + targets/hal/TARGET_STM/TARGET_STM32F7/sleep.c | 61 + .../hal/TARGET_STM/TARGET_STM32F7/spi_api.c | 320 + .../hal/TARGET_STM/TARGET_STM32F7/us_ticker.c | 70 + .../TARGET_STM32L0/PeripheralPins.h | 66 + .../TARGET_DISCO_L053C8/PeripheralNames.h | 77 + .../TARGET_DISCO_L053C8/PeripheralPins.c | 156 + .../TARGET_DISCO_L053C8/PinNames.h | 181 + .../TARGET_DISCO_L053C8/PortNames.h | 48 + .../TARGET_DISCO_L053C8/device.h | 70 + .../TARGET_DISCO_L053C8/objects.h | 113 + .../TARGET_DISCO_L053C8/rtc_api.c | 215 + .../TARGET_NUCLEO_L053R8/PeripheralNames.h | 77 + .../TARGET_NUCLEO_L053R8/PeripheralPins.c | 170 + .../TARGET_NUCLEO_L053R8/PinNames.h | 194 + .../TARGET_NUCLEO_L053R8/PortNames.h | 48 + .../TARGET_NUCLEO_L053R8/device.h | 70 + .../TARGET_NUCLEO_L053R8/objects.h | 113 + .../TARGET_NUCLEO_L053R8/rtc_api.c | 203 + .../TARGET_NUCLEO_L073RZ/PeripheralNames.h | 81 + .../TARGET_NUCLEO_L073RZ/PeripheralPins.c | 206 + .../TARGET_NUCLEO_L073RZ/PinNames.h | 194 + .../TARGET_NUCLEO_L073RZ/PortNames.h | 48 + .../TARGET_NUCLEO_L073RZ/device.h | 70 + .../TARGET_NUCLEO_L073RZ/objects.h | 113 + .../TARGET_NUCLEO_L073RZ/rtc_api.c | 203 + .../TARGET_STM/TARGET_STM32L0/analogin_api.c | 185 + .../TARGET_STM/TARGET_STM32L0/analogout_api.c | 168 + .../hal/TARGET_STM/TARGET_STM32L0/gpio_api.c | 77 + .../TARGET_STM/TARGET_STM32L0/gpio_irq_api.c | 267 + .../TARGET_STM/TARGET_STM32L0/gpio_object.h | 76 + .../hal/TARGET_STM/TARGET_STM32L0/i2c_api.c | 413 + .../TARGET_STM32L0/mbed_overrides.c | 35 + .../hal/TARGET_STM/TARGET_STM32L0/pinmap.c | 150 + .../hal/TARGET_STM/TARGET_STM32L0/port_api.c | 103 + .../TARGET_STM/TARGET_STM32L0/pwmout_api.c | 183 + .../TARGET_STM/TARGET_STM32L0/serial_api.c | 409 + targets/hal/TARGET_STM/TARGET_STM32L0/sleep.c | 61 + .../hal/TARGET_STM/TARGET_STM32L0/spi_api.c | 268 + .../hal/TARGET_STM/TARGET_STM32L0/us_ticker.c | 113 + .../TARGET_STM32L1/PeripheralPins.h | 66 + .../TARGET_MOTE_L152RC/PeripheralNames.h | 82 + .../TARGET_MOTE_L152RC/PeripheralPins.c | 188 + .../TARGET_MOTE_L152RC/PinNames.h | 183 + .../TARGET_MOTE_L152RC/PortNames.h | 48 + .../TARGET_MOTE_L152RC/device.h | 70 + .../TARGET_MOTE_L152RC/objects.h | 110 + .../TARGET_NUCLEO_L152RE/PeripheralNames.h | 84 + .../TARGET_NUCLEO_L152RE/PeripheralPins.c | 192 + .../TARGET_NUCLEO_L152RE/PinNames.h | 183 + .../TARGET_NUCLEO_L152RE/PortNames.h | 48 + .../TARGET_NUCLEO_L152RE/device.h | 70 + .../TARGET_NUCLEO_L152RE/objects.h | 110 + .../TARGET_NZ32SC151/PeripheralNames.h | 95 + .../TARGET_NZ32SC151/PeripheralPins.c | 192 + .../TARGET_NZ32SC151/PinNames.h | 176 + .../TARGET_NZ32SC151/PortNames.h | 48 + .../TARGET_STM32L1/TARGET_NZ32SC151/device.h | 70 + .../TARGET_STM32L1/TARGET_NZ32SC151/objects.h | 110 + .../TARGET_STM/TARGET_STM32L1/analogin_api.c | 193 + .../TARGET_STM/TARGET_STM32L1/analogout_api.c | 146 + .../hal/TARGET_STM/TARGET_STM32L1/gpio_api.c | 77 + .../TARGET_STM/TARGET_STM32L1/gpio_irq_api.c | 332 + .../TARGET_STM/TARGET_STM32L1/gpio_object.h | 79 + .../hal/TARGET_STM/TARGET_STM32L1/i2c_api.c | 480 + .../TARGET_STM32L1/mbed_overrides.c | 35 + .../hal/TARGET_STM/TARGET_STM32L1/pinmap.c | 143 + .../hal/TARGET_STM/TARGET_STM32L1/port_api.c | 103 + .../TARGET_STM/TARGET_STM32L1/pwmout_api.c | 201 + .../hal/TARGET_STM/TARGET_STM32L1/rtc_api.c | 209 + .../TARGET_STM/TARGET_STM32L1/serial_api.c | 396 + targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c | 98 + .../hal/TARGET_STM/TARGET_STM32L1/spi_api.c | 293 + .../hal/TARGET_STM/TARGET_STM32L1/us_ticker.c | 69 + .../TARGET_EFM32GG_STK3700/Modules.h | 28 + .../TARGET_EFM32GG_STK3700/PeripheralNames.h | 70 + .../TARGET_EFM32GG_STK3700/PeripheralPins.c | 220 + .../TARGET_EFM32GG_STK3700/PeripheralPins.h | 49 + .../TARGET_EFM32GG_STK3700/PinNames.h | 113 + .../TARGET_EFM32GG_STK3700/PortNames.h | 37 + .../TARGET_EFM32GG_STK3700/device.h | 56 + .../device_peripherals.h | 79 + .../TARGET_EFM32HG_STK3400/Modules.h | 28 + .../TARGET_EFM32HG_STK3400/PeripheralNames.h | 59 + .../TARGET_EFM32HG_STK3400/PeripheralPins.c | 168 + .../TARGET_EFM32HG_STK3400/PeripheralPins.h | 45 + .../TARGET_EFM32HG_STK3400/PinNames.h | 112 + .../TARGET_EFM32HG_STK3400/PortNames.h | 37 + .../TARGET_EFM32HG_STK3400/device.h | 62 + .../device_peripherals.h | 79 + .../TARGET_EFM32LG_STK3600/Modules.h | 28 + .../TARGET_EFM32LG_STK3600/PeripheralNames.h | 70 + .../TARGET_EFM32LG_STK3600/PeripheralPins.c | 220 + .../TARGET_EFM32LG_STK3600/PeripheralPins.h | 49 + .../TARGET_EFM32LG_STK3600/PinNames.h | 112 + .../TARGET_EFM32LG_STK3600/PortNames.h | 37 + .../TARGET_EFM32LG_STK3600/device.h | 57 + .../device_peripherals.h | 79 + .../TARGET_EFM32WG_STK3800/Modules.h | 28 + .../TARGET_EFM32WG_STK3800/PeripheralNames.h | 70 + .../TARGET_EFM32WG_STK3800/PeripheralPins.c | 220 + .../TARGET_EFM32WG_STK3800/PeripheralPins.h | 49 + .../TARGET_EFM32WG_STK3800/PinNames.h | 112 + .../TARGET_EFM32WG_STK3800/PortNames.h | 37 + .../TARGET_EFM32WG_STK3800/device.h | 57 + .../device_peripherals.h | 79 + .../TARGET_EFM32ZG_STK3200/Modules.h | 28 + .../TARGET_EFM32ZG_STK3200/PeripheralNames.h | 57 + .../TARGET_EFM32ZG_STK3200/PeripheralPins.c | 119 + .../TARGET_EFM32ZG_STK3200/PeripheralPins.h | 45 + .../TARGET_EFM32ZG_STK3200/PinNames.h | 112 + .../TARGET_EFM32ZG_STK3200/PortNames.h | 37 + .../TARGET_EFM32ZG_STK3200/device.h | 62 + .../device_peripherals.h | 79 + .../TARGET_EFM32/analogin_api.c | 130 + .../TARGET_EFM32/analogout_api.c | 141 + .../TARGET_EFM32/clocking.h | 58 + .../TARGET_EFM32/dma_api.c | 89 + .../TARGET_EFM32/dma_api_HAL.h | 62 + .../TARGET_EFM32/emlib/Changes_emlib.txt | 327 + .../TARGET_EFM32/emlib/ReadMe_emlib.txt | 72 + .../TARGET_EFM32/emlib/inc/em_acmp.h | 413 + .../TARGET_EFM32/emlib/inc/em_adc.h | 586 + .../TARGET_EFM32/emlib/inc/em_aes.h | 247 + .../TARGET_EFM32/emlib/inc/em_assert.h | 80 + .../TARGET_EFM32/emlib/inc/em_bitband.h | 188 + .../TARGET_EFM32/emlib/inc/em_burtc.h | 418 + .../TARGET_EFM32/emlib/inc/em_chip.h | 194 + .../TARGET_EFM32/emlib/inc/em_cmu.h | 928 + .../TARGET_EFM32/emlib/inc/em_common.h | 116 + .../TARGET_EFM32/emlib/inc/em_dac.h | 392 + .../TARGET_EFM32/emlib/inc/em_dbg.h | 93 + .../TARGET_EFM32/emlib/inc/em_dma.h | 463 + .../TARGET_EFM32/emlib/inc/em_ebi.h | 820 + .../TARGET_EFM32/emlib/inc/em_emu.h | 470 + .../TARGET_EFM32/emlib/inc/em_gpio.h | 698 + .../TARGET_EFM32/emlib/inc/em_i2c.h | 492 + .../TARGET_EFM32/emlib/inc/em_idac.h | 274 + .../TARGET_EFM32/emlib/inc/em_int.h | 122 + .../TARGET_EFM32/emlib/inc/em_lcd.h | 633 + .../TARGET_EFM32/emlib/inc/em_lesense.h | 1339 ++ .../TARGET_EFM32/emlib/inc/em_letimer.h | 268 + .../TARGET_EFM32/emlib/inc/em_leuart.h | 281 + .../TARGET_EFM32/emlib/inc/em_mpu.h | 242 + .../TARGET_EFM32/emlib/inc/em_msc.h | 434 + .../TARGET_EFM32/emlib/inc/em_opamp.h | 570 + .../TARGET_EFM32/emlib/inc/em_part.h | 41 + .../TARGET_EFM32/emlib/inc/em_pcnt.h | 503 + .../TARGET_EFM32/emlib/inc/em_prs.h | 131 + .../TARGET_EFM32/emlib/inc/em_rmu.h | 90 + .../TARGET_EFM32/emlib/inc/em_rtc.h | 191 + .../TARGET_EFM32/emlib/inc/em_system.h | 304 + .../TARGET_EFM32/emlib/inc/em_timer.h | 922 + .../TARGET_EFM32/emlib/inc/em_usart.h | 841 + .../TARGET_EFM32/emlib/inc/em_vcmp.h | 361 + .../TARGET_EFM32/emlib/inc/em_version.h | 69 + .../TARGET_EFM32/emlib/inc/em_wdog.h | 155 + .../TARGET_EFM32/emlib/src/em_acmp.c | 320 + .../TARGET_EFM32/emlib/src/em_adc.c | 524 + .../TARGET_EFM32/emlib/src/em_aes.c | 1389 ++ .../TARGET_EFM32/emlib/src/em_assert.c | 69 + .../TARGET_EFM32/emlib/src/em_burtc.c | 314 + .../TARGET_EFM32/emlib/src/em_cmu.c | 2502 +++ .../TARGET_EFM32/emlib/src/em_dac.c | 341 + .../TARGET_EFM32/emlib/src/em_dbg.c | 119 + .../TARGET_EFM32/emlib/src/em_dma.c | 1230 ++ .../TARGET_EFM32/emlib/src/em_ebi.c | 1173 ++ .../TARGET_EFM32/emlib/src/em_emu.c | 716 + .../TARGET_EFM32/emlib/src/em_gpio.c | 249 + .../TARGET_EFM32/emlib/src/em_i2c.c | 813 + .../TARGET_EFM32/emlib/src/em_idac.c | 281 + .../TARGET_EFM32/emlib/src/em_int.c | 73 + .../TARGET_EFM32/emlib/src/em_lcd.c | 766 + .../TARGET_EFM32/emlib/src/em_lesense.c | 1159 ++ .../TARGET_EFM32/emlib/src/em_letimer.c | 533 + .../TARGET_EFM32/emlib/src/em_leuart.c | 702 + .../TARGET_EFM32/emlib/src/em_mpu.c | 125 + .../TARGET_EFM32/emlib/src/em_msc.c | 770 + .../TARGET_EFM32/emlib/src/em_opamp.c | 431 + .../TARGET_EFM32/emlib/src/em_pcnt.c | 763 + .../TARGET_EFM32/emlib/src/em_prs.c | 133 + .../TARGET_EFM32/emlib/src/em_rmu.c | 247 + .../TARGET_EFM32/emlib/src/em_rtc.c | 377 + .../TARGET_EFM32/emlib/src/em_system.c | 119 + .../TARGET_EFM32/emlib/src/em_timer.c | 262 + .../TARGET_EFM32/emlib/src/em_usart.c | 1159 ++ .../TARGET_EFM32/emlib/src/em_vcmp.c | 185 + .../TARGET_EFM32/emlib/src/em_wdog.c | 225 + .../TARGET_Silicon_Labs/TARGET_EFM32/error.h | 66 + .../TARGET_EFM32/gpio_api.c | 123 + .../TARGET_EFM32/gpio_irq_api.c | 220 + .../TARGET_EFM32/i2c_api.c | 557 + .../TARGET_EFM32/lp_ticker.c | 83 + .../TARGET_EFM32/mbed_overrides.c | 112 + .../TARGET_EFM32/objects.h | 150 + .../TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c | 48 + .../TARGET_EFM32/pinmap_function.c | 56 + .../TARGET_EFM32/pinmap_function.h | 47 + .../TARGET_EFM32/port_api.c | 95 + .../TARGET_EFM32/pwmout_api.c | 207 + .../TARGET_EFM32/rtc_api.c | 163 + .../TARGET_EFM32/rtc_api_HAL.h | 45 + .../TARGET_EFM32/serial_api.c | 1733 ++ .../TARGET_Silicon_Labs/TARGET_EFM32/sleep.c | 100 + .../TARGET_EFM32/sleepmodes.h | 32 + .../TARGET_EFM32/spi_api.c | 1109 ++ .../TARGET_EFM32/us_ticker.c | 205 + .../TARGET_W7500x/PeripheralPins.h | 60 + .../TARGET_WIZwiki_W7500/PeripheralNames.h | 78 + .../TARGET_WIZwiki_W7500/PeripheralPins.c | 124 + .../TARGET_WIZwiki_W7500/PinNames.h | 231 + .../TARGET_WIZwiki_W7500/PortNames.h | 48 + .../TARGET_WIZwiki_W7500/device.h | 74 + .../TARGET_WIZwiki_W7500/objects.h | 103 + .../TARGET_W7500x/analogin_api.c | 116 + .../TARGET_WIZNET/TARGET_W7500x/gpio_api.c | 71 + .../TARGET_W7500x/gpio_irq_api.c | 175 + .../TARGET_WIZNET/TARGET_W7500x/gpio_object.h | 101 + .../hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c | 349 + .../TARGET_W7500x/mbed_overrides.c | 38 + .../hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c | 135 + .../TARGET_WIZNET/TARGET_W7500x/port_api.c | 111 + .../TARGET_WIZNET/TARGET_W7500x/pwmout_api.c | 144 + .../hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c | 79 + .../TARGET_WIZNET/TARGET_W7500x/serial_api.c | 310 + .../hal/TARGET_WIZNET/TARGET_W7500x/sleep.c | 42 + .../hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c | 202 + .../TARGET_WIZNET/TARGET_W7500x/us_ticker.c | 134 + 3816 files changed, 1862154 insertions(+) create mode 100644 CMakeLists.txt create mode 100644 api/AnalogIn.h create mode 100644 api/AnalogOut.h create mode 100644 api/BusIn.h create mode 100644 api/BusInOut.h create mode 100644 api/BusOut.h create mode 100644 api/CAN.h create mode 100644 api/CThunk.h create mode 100644 api/CallChain.h create mode 100644 api/CircularBuffer.h create mode 100644 api/DigitalIn.h create mode 100644 api/DigitalInOut.h create mode 100644 api/DigitalOut.h create mode 100644 api/DirHandle.h create mode 100644 api/Ethernet.h create mode 100644 api/FileBase.h create mode 100644 api/FileHandle.h create mode 100644 api/FileLike.h create mode 100644 api/FilePath.h create mode 100644 api/FileSystemLike.h create mode 100644 api/FunctionPointer.h create mode 100644 api/I2C.h create mode 100644 api/I2CSlave.h create mode 100644 api/InterruptIn.h create mode 100644 api/InterruptManager.h create mode 100644 api/LocalFileSystem.h create mode 100644 api/LowPowerTicker.h create mode 100644 api/LowPowerTimeout.h create mode 100644 api/LowPowerTimer.h create mode 100644 api/PortIn.h create mode 100644 api/PortInOut.h create mode 100644 api/PortOut.h create mode 100644 api/PwmOut.h create mode 100644 api/RawSerial.h create mode 100644 api/SPI.h create mode 100644 api/SPISlave.h create mode 100644 api/Serial.h create mode 100644 api/SerialBase.h create mode 100644 api/Stream.h create mode 100644 api/Ticker.h create mode 100644 api/Timeout.h create mode 100644 api/Timer.h create mode 100644 api/TimerEvent.h create mode 100644 api/Transaction.h create mode 100644 api/can_helper.h create mode 100644 api/mbed.h create mode 100644 api/mbed_assert.h create mode 100644 api/mbed_debug.h create mode 100644 api/mbed_error.h create mode 100644 api/mbed_interface.h create mode 100644 api/platform.h create mode 100644 api/rtc_time.h create mode 100644 api/semihost_api.h create mode 100644 api/toolchain.h create mode 100644 api/wait_api.h create mode 100644 common/BusIn.cpp create mode 100644 common/BusInOut.cpp create mode 100644 common/BusOut.cpp create mode 100644 common/CAN.cpp create mode 100644 common/CallChain.cpp create mode 100644 common/Ethernet.cpp create mode 100644 common/FileBase.cpp create mode 100644 common/FileLike.cpp create mode 100644 common/FilePath.cpp create mode 100644 common/FileSystemLike.cpp create mode 100644 common/I2C.cpp create mode 100644 common/I2CSlave.cpp create mode 100644 common/InterruptIn.cpp create mode 100644 common/InterruptManager.cpp create mode 100644 common/LocalFileSystem.cpp create mode 100644 common/RawSerial.cpp create mode 100644 common/SPI.cpp create mode 100644 common/SPISlave.cpp create mode 100644 common/Serial.cpp create mode 100644 common/SerialBase.cpp create mode 100644 common/Stream.cpp create mode 100644 common/Ticker.cpp create mode 100644 common/Timeout.cpp create mode 100644 common/Timer.cpp create mode 100644 common/TimerEvent.cpp create mode 100644 common/assert.c create mode 100644 common/board.c create mode 100644 common/error.c create mode 100644 common/gpio.c create mode 100644 common/lp_ticker_api.c create mode 100644 common/mbed_interface.c create mode 100644 common/pinmap_common.c create mode 100644 common/retarget.cpp create mode 100644 common/rtc_time.c create mode 100644 common/semihost_api.c create mode 100644 common/ticker_api.c create mode 100644 common/us_ticker_api.c create mode 100644 common/wait_api.c create mode 100644 hal/analogin_api.h create mode 100644 hal/analogout_api.h create mode 100644 hal/buffer.h create mode 100644 hal/can_api.h create mode 100644 hal/dma_api.h create mode 100644 hal/ethernet_api.h create mode 100644 hal/gpio_api.h create mode 100644 hal/gpio_irq_api.h create mode 100644 hal/i2c_api.h create mode 100644 hal/lp_ticker_api.h create mode 100644 hal/pinmap.h create mode 100644 hal/port_api.h create mode 100644 hal/pwmout_api.h create mode 100644 hal/rtc_api.h create mode 100644 hal/serial_api.h create mode 100644 hal/sleep_api.h create mode 100644 hal/spi_api.h create mode 100644 hal/ticker_api.h create mode 100644 hal/us_ticker_api.h create mode 100644 module.json create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/TOOLCHAIN_ARM_STD/startup_MPS2.s create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/SMM_MPS2.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/TOOLCHAIN_ARM_STD/startup_MPS2.s create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/peripherallink.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/system_CMSDK_CM0plus.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/CMSDK_CM3.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/TOOLCHAIN_ARM_STD/startup_MPS2.s create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/peripherallink.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/system_CMSDK_CM3.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/SMM_MPS2.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/TOOLCHAIN_ARM_STD/startup_MPS2.s create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/peripherallink.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/system_CMSDK_CM4.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/CMSDK_CM7.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/gcc_arm.ld create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/TOOLCHAIN_GCC_ARM/startup_ARMCM7.s create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/peripherallink.h create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.c create mode 100644 targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/system_CMSDK_CM7.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/startup_samd21.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/TOOLCHAIN_IAR/startup_samd21.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/system_samd21.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/startup_samr21.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.c create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/system_samr21.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_ac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dsu.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_evsys.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_hmatrixb.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_i2s.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_pm.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_port.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rfctrl.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sercom.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_sysctrl.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tcc.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_usb.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_wdt.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_ac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dmac.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_dsu.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_eic.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_evsys.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_gclk.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_mtb.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_nvmctrl.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac0.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac1.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pac2.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_pm.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rfctrl.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_rtc.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sbmatrix.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom0.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom1.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom2.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom3.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom4.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sercom5.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_sysctrl.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc3.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc4.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc5.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc6.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tc7.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc0.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc2.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_usb.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_wdt.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samd21j18a.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/pio/pio_samr21g18a.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samd21j18a.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/samr21g18a.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/compiler.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/header_files/io.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrecursion.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/mrepeat.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/preprocessor.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/stringz.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/preprocessor/tpaste.h create mode 100644 targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/status_codes.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/MKL26Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_ARM_MICRO/MKL26Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_GCC_ARM/MKL26Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_GCC_ARM/startup_MKL26Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_IAR/MKL26Z4.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_IAR/startup_MKL26Z4.s create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/MK64F.sct create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/startup_MK64F12.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/K64FN1M0xxx12.ld create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_GCC_ARM/startup_MK64F12.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/MK64F.icf create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/TOOLCHAIN_IAR/startup_MK64F12.S create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c create mode 100644 targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.S create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.S create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/MAX32610.sct create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/startup_MAX32610.S create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/max32610.ld create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/MAX32610.icf create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_IAR/startup_MAX32610.S create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/adc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/aes_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/afe_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/clkman_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/crc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/icc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/maa_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pt_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tpu_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/trim_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/uart_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/usb_regs.h create mode 100644 targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.S create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/compiler_abstraction.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf_delay.h create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.c create mode 100644 targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/system_nrf51.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/LPC11U68.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U68/startup_LPC11U6x.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/LPC11U68.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_ARM/TARGET_LPC11U68/startup_LPC11U68.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/LPC11U68.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/aeabi_romdiv_patch.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/mtb.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_GCC_CR/TARGET_LPC11U68/startup_LPC11U68.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/LPC11U68.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_APPNEARME_MICRONFCBOARD/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/LPC11U24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_301/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/LPC11U24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U24_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/LPC11U34.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U34_421/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/LPC11U35.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/LPC11U35.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U35_501/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/LPC11U37.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37_501/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/LPC11U24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_OC_MBUINO/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_APPNEARME_MICRONFCBOARD/LPC11U34.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_301/LPC11U24.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U24_401/LPC11U24.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U34_421/LPC11U34.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_401/LPC11U35.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_501/LPC11U35.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U35_Y5_MBUG/LPC11U35.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37_501/LPC11U37.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPCCAPPUCCINO/LPC11U37.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_OC_MBUINO/LPC11U24.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld create mode 100755 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/LPC11U24.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/LPC11U24.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/LPC11U24.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/LPC11U35.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_401/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/LPC11U35.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U35_501/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/LPC11U37.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U37_501/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/LPC11U24.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_OC_MBUINO/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/power_api.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/system_LPC11xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/LPC1114.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11XX/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/LPC11C24.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11CXX/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11CXX/LPC11C24.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_GCC_CS/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/LPC11C24.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11CXX/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/LPC1114.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/bitfields.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/system_LPC11xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/LPC1347.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/startup_LPC13xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/LPC1347.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/startup_LPC13xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/LPC1347.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/LPC1347.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_IAR/startup_LPC1347.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/LPC1549.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/startup_LPC15xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/LPC1549.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/LPC15xx.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_IAR/startup_LPC15xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/LPC1768.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/LPC1768.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/startup_LPC17xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/LPC1768.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/TARGET_XBED_LPC1768/XBED_LPC1768.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/LPC1768.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/startup_LPC17xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/startup_LPC17xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/LPC2368.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_functions.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_table.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/LPC2368.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_functions.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_table.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/LPC2368.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_functions.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_table.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/LPC2368.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_functions.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_table.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/LPC2368.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_functions.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_table.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_realmonitor.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/LPC24xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/LPC2460.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_functions.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/TOOLCHAIN_GCC_ARM/vector_table.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/core_arm7.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/system_LPC24xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_defns.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC2460/vector_realmonitor.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/LPC407X_8X.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_ARM_STD/sys_helper.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/LPC4088.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_ARM/startup_LPC408x.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/LPC407x_8x.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/LPC4088.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/TOOLCHAIN_IAR/startup_LPC408x.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/LPC43xx.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4330/startup_LPC43xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/LPC4337.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/TARGET_LPC4337/startup_LPC4337.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/LPC4330.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_ARM/startup_LPC43xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/LPC43xx.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_IAR/startup_LPC43xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/LPC810.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/TOOLCHAIN_IAR/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/LPC812.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_IAR/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/LPC824.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/LPC824.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/LPC824.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.S create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_NXP/TARGET_LPC82X/system_LPC82x.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.S create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/intc_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/riic_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/scif_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/usb_iobitmask.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/rza_io_regrw.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/nvic_wrapper.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/rza_io_regrw.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c create mode 100644 targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/Release_Notes_stm32f0xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/STM32F0xx.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/TOOLCHAIN_GCC_ARM/startup_stm32f051x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/startup_stm32f030x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/startup_stm32f030x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/STM32F030X8.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_GCC_ARM/startup_stm32f030x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/startup_stm32f030x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/startup_stm32f070xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/stm32f070xb.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/startup_stm32f070xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/stm32f070xb.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/STM32F070XB.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_GCC_ARM/startup_stm32f070xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/startup_stm32f070xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/startup_stm32f072xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/stm32f072rb.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/startup_stm32f072xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/stm32f072rb.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/STM32F072XB.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_GCC_ARM/startup_stm32f072xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/startup_stm32f072xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/startup_stm32f091rc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/stm32f091rc.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/startup_stm32f091rc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/stm32f091rc.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/STM32F091XC.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/startup_stm32f091xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/Release_Notes_stm32f1xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/STM32F100.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/TOOLCHAIN_GCC_ARM/startup_stm32f100xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/startup_stm32f103xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f103xb.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/startup_stm32f103xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/stm32f103xb.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/startup_stm32f103xb.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f103xb.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f103xb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/stm32f1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/system_stm32f1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_can_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cec.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_dma_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_hcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nor.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pccard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_sdmmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_sdmmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_usb.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_usb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/Release_Notes_stm32f3xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/STM32F303XC.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/TOOLCHAIN_GCC_ARM/startup_stm32f303xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/stm32f303xc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/system_stm32f3xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/system_stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_ARM_MICRO/stm32f334x8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_ARM_STD/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_ARM_STD/stm32f334x8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/STM32F334X8.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_IAR/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/TOOLCHAIN_IAR/stm32f334x8.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/stm32f334x8.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/system_stm32f3xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/system_stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/startup_stm32f302x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/stm32f302x8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/STM32F302X8.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_IAR/startup_stm32f302x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/TOOLCHAIN_IAR/stm32f302x8.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/stm32f302x8.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/system_stm32f3xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/system_stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/stm32f303xe.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/STM32F303XE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_IAR/startup_stm32f303xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/TOOLCHAIN_IAR/stm32f303xe.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/stm32f303xe.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/system_stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/stm32f334r8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/stm32f334r8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_GCC_ARM/STM32F334x8.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_IAR/startup_stm32f334x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/TOOLCHAIN_IAR/stm32f334x8.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/stm32f334x8.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/system_stm32f3xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/system_stm32f3xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_can.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_comp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_crc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2c_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_i2s_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_irda_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_opamp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pccard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_pwr_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sdadc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smartcard_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_smbus.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_sram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tsc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_uart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_usart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_ll_fmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_ll_fmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/stm32f302x8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/startup_stm32f302x8.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/stm32f302x8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_GCC_ARM/STM32F3XX.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/TOOLCHAIN_GCC_ARM/startup_STM32F30x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_can.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_can.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_exti.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_exti.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_misc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_misc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_opamp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_opamp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/Release_Notes_stm32f4xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/TOOLCHAIN_GCC_ARM/STM32F401XC.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_IAR/startup_stm32f429xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/TOOLCHAIN_IAR/stm32f429xx_flash.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/startup_STM32F41x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f411xe.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_MICRO/stm32f405xx.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_STD/startup_stm32f405xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_STD/stm32f405xx.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_GCC_ARM/STM32F405.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_GCC_ARM/startup_STM32F40x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_IAR/startup_stm32f405xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_IAR/stm32f405xx.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f405xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f411xe.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/stm32f401xe.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/startup_stm32f401xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/stm32f401xe.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_GCC_ARM/STM32F401XE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_IAR/startup_stm32f401xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/TOOLCHAIN_IAR/stm32f401xe.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f401xe.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_IAR/startup_stm32f411xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f411xe.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/STM32F446XE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/TOOLCHAIN_GCC_ARM/startup_stm32f446xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_ARM_MICRO/STM32F407.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_ARM_MICRO/startup_STM32F40x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_ARM_STD/STM32F407.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_ARM_STD/startup_STM32F40x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_GCC_ARM/STM32F407XG.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f407xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407VG/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/stm32f439xx.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/STM32F439ZI.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/startup_stm32f439xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/TOOLCHAIN_IAR/stm32f439xx_flash.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f4xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32_hal_legacy.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_can.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cec.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_cryp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dcmi_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_flash_ramfunc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_fmpi2c_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_hcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2c_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_ltdc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_msp_template.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nor.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pccard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_qspi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rng.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sai_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sdram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spdifrx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_sram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_sdmmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_usb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_ARM_STD/STM32F407.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_ARM_STD/startup_STM32F40x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_GCC_ARM/STM32F407.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_GCC_ARM/startup_STM32F40x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_IAR/STM32F407.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/TOOLCHAIN_IAR/startup_STM32F40x.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F4XX/system_stm32f4xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/stm32f746ng.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/startup_stm32f746ng.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/stm32f746ng.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/STM32F746NG.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/startup_stm32f746xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f746ng.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f746xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/stm32f7xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sai_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_smartcard_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_usart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_usb.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/stm32l053c8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/stm32l053c8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_GCC_ARM/STM32L053X8.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_IAR/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_IAR/stm32l053xx.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/stm32l053r8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/stm32l053r8.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/STM32L053X8.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/stm32l053xx.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/stm32l073xz.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_GCC_ARM/STM32L073XZ.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_IAR/startup_stm32l073xx.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_IAR/stm32l073xx.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l073xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S create mode 100755 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c create mode 100755 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h create mode 100755 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx.h create mode 100755 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l152re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l152re.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/STM32L152XE.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/stm32l152xe.icf create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/stm32l151rc.sct create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/STM32L151XC.ld create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l151xc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_conf.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.c create mode 100644 targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/efm32gg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_MICRO/startup_efm32gg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/efm32gg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_ARM_STD/startup_efm32gg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/efm32gg.ld create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/TOOLCHAIN_GCC_ARM/startup_efm32gg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/cmsis.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg990f1024.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_acmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_adc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_aes.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_pins.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_af_ports.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_burtc_ret.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_calibrate.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_cmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dac.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_devinfo.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dma_descriptor.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmactrl.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmareq.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_ebi.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_emu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_etm.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_gpio_p.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_i2c.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lcd.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_buf.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lesense_st.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_letimer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_leuart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_msc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_pcnt.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_prs_signals.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_romtable.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_rtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_timer_cc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_uart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_diep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_doep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_usb_hc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_vcmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_wdog.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/em_device.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/system_efm32gg.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/efm32hg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_ARM_MICRO/startup_efm32hg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg.ld create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/startup_efm32hg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/arm_math.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/cmsis.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_acmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_adc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_aes.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_pins.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_af_ports.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_calibrate.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_cmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_devinfo.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma_descriptor.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmactrl.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dmareq.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_emu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_gpio_p.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_i2c.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_idac.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_leuart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_msc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_mtb.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_pcnt.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs_signals.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_romtable.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_rtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_timer_cc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_diep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usb_doep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_vcmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_wdog.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/em_device.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/system_efm32hg.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_MICRO/efm32lg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_MICRO/startup_efm32lg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/efm32lg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/startup_efm32lg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/efm32lg.ld create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/startup_efm32lg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/cmsis.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg990f256.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_acmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_adc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_aes.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_af_pins.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_af_ports.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_burtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_burtc_ret.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_calibrate.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_cmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dac.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_devinfo.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dma_descriptor.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dmactrl.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dmareq.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_ebi.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_emu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_etm.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_gpio.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_gpio_p.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_i2c.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lcd.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_buf.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_lesense_st.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_letimer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_leuart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_msc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_pcnt.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_prs_signals.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_romtable.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_timer_cc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_uart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_diep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_doep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_usb_hc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_vcmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_wdog.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/em_device.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/system_efm32lg.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/system_efm32lg.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_MICRO/efm32wg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_MICRO/startup_efm32wg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/efm32wg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/startup_efm32wg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_GCC_ARM/efm32wg.ld create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/TOOLCHAIN_GCC_ARM/startup_efm32wg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/cmsis.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg990f256.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_acmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_adc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_aes.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_af_pins.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_af_ports.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_burtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_burtc_ret.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_calibrate.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_cmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dac.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_devinfo.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dma_descriptor.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dmactrl.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_dmareq.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_ebi.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_emu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_etm.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_fpueh.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_gpio.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_gpio_p.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_i2c.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lcd.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_buf.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_lesense_st.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_letimer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_leuart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_msc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_pcnt.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_prs_signals.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_romtable.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_timer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_timer_cc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_uart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_diep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_doep.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_usb_hc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_vcmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_wdog.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/em_device.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/system_efm32wg.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/system_efm32wg.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_MICRO/efm32zg.sct create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_ARM_MICRO/startup_efm32zg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/efm32zg.ld create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/startup_efm32zg.S create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/arm_math.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/cmsis.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg222f32.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_acmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_adc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_aes.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_af_pins.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_af_ports.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_calibrate.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_cmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_devinfo.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dma_descriptor.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dmactrl.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_dmareq.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_emu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_gpio.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_gpio_p.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_i2c.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_idac.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_leuart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_msc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_pcnt.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs_ch.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_prs_signals.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_rmu.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_romtable.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_rtc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_timer.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_timer_cc.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_usart.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_vcmp.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/efm32zg_wdog.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/em_device.h create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/system_efm32zg.c create mode 100644 targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/system_efm32zg.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.S create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.S create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.S create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_dualtimer.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_dualtimer.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c create mode 100644 targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h create mode 100644 targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S create mode 100644 targets/cmsis/TOOLCHAIN_IAR/cmain.S create mode 100644 targets/cmsis/core_ca9.h create mode 100644 targets/cmsis/core_caFunc.h create mode 100644 targets/cmsis/core_caInstr.h create mode 100644 targets/cmsis/core_ca_mmu.h create mode 100644 targets/cmsis/core_cm0.h create mode 100644 targets/cmsis/core_cm0plus.h create mode 100644 targets/cmsis/core_cm3.h create mode 100644 targets/cmsis/core_cm4.h create mode 100644 targets/cmsis/core_cm4_simd.h create mode 100644 targets/cmsis/core_cm7.h create mode 100644 targets/cmsis/core_cmFunc.h create mode 100644 targets/cmsis/core_cmInstr.h create mode 100644 targets/cmsis/core_cmSimd.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PeripheralNames.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PinNames.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/PortNames.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/fpga.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/device.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/gpio_object.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/i2c_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/objects.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/pinmap.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/port_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_api.c create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h create mode 100644 targets/hal/TARGET_ARM_SSG/TARGET_MPS2/us_ticker.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralNames.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/PeripheralPins.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/PinNames.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/PortNames.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMD21J18A/device.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/PeripheralPins.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/TARGET_SAMR21G18A/device.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/analogin_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/dma_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/dma_api_HAL.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/adc/adc_sam_d_r/adc_feature.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/dma_crc.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/dma/quick_start/qs_dma_basic.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_callback.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/extint/extint_sam_d_r/extint.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/port.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/port/quick_start/qs_port_basic.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_count.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/rtc/rtc_sam_d_r/rtc_count.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_common.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_master.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_master.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_samd21_r21_d10_d11_l21/i2c_slave.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/i2c_slave.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave/qs_i2c_slave_basic_use.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/i2c/quick_start_slave_dma/qs_i2c_slave_dma.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_interrupt.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/sercom_pinout.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/sercom/usart/usart_interrupt.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_config_check.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/gclk.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/gclk.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/pinmux.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/pinmux/quick_start/qs_pinmux_basic.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/power/power_sam_d_r/power.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/reset/reset_sam_d_r/reset.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/system.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_interrupt.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/tc/tc_sam_d_r/tc.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/gpio_object.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/objects.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/pinmap.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/pinmap_function.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/pinmap_function.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/port_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/rtc_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/sercom_dma.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/sercom_dma.h create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/serial_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/sleep_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/spi_api.c create mode 100644 targets/hal/TARGET_Atmel/TARGET_SAM21/us_ticker.c create mode 100644 targets/hal/TARGET_Atmel/common/boards/board.h create mode 100644 targets/hal/TARGET_Atmel/common/utils/interrupt.h create mode 100644 targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.c create mode 100644 targets/hal/TARGET_Atmel/common/utils/interrupt/interrupt_sam_nvic.h create mode 100644 targets/hal/TARGET_Atmel/common/utils/parts.h create mode 100644 targets/hal/TARGET_Atmel/common2/services/delay/delay.h create mode 100644 targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.c create mode 100644 targets/hal/TARGET_Atmel/common2/services/delay/sam0/systick_counter.h create mode 100644 targets/hal/TARGET_Atmel/config/conf_board.h create mode 100644 targets/hal/TARGET_Atmel/config/conf_clocks.h create mode 100644 targets/hal/TARGET_Atmel/config/conf_dma.h create mode 100644 targets/hal/TARGET_Atmel/config/conf_extint.h create mode 100644 targets/hal/TARGET_Atmel/config/conf_spi.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/PeripheralPins.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/PortNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/analogin_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/analogout_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/gpio_object.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/i2c_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/pinmap.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/port_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/rtc_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_K20XX/us_ticker.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/PeripheralPins.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/PortNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/analogin_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/analogout_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/clk_freqs.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/gpio_object.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/i2c_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/objects.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/pinmap.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/port_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/pwmout_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KLXX/us_ticker.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PeripheralPins.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/PortNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_clock_K22F51212.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/MK22F51212/fsl_sim_hal_K22F51212.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_adc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_aips.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_cmp.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_crc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dmamux.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fmc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_gpio.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2c.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lptmr.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcg.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_nv.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_osc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pit.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pmc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rcm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfsys.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rfvbat.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rng.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_rtc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_sim.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_uart.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_usb.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_vref.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_wdog.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/fsl_bitaccess.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/fsl_device_registers.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/common/phyksz8081/fsl_phy_driver.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/clock/fsl_clock_manager.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_driver.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/fsl_enet_rtcs_adapter.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/src/fsl_enet_irq.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/enet/subdir.mk create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/interrupt/fsl_interrupt_manager.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/common/fsl_pit_common.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/fsl_pit_driver.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_driver.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/drivers/pit/src/fsl_pit_irq.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dac/fsl_dac_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dmamux/fsl_dmamux_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/gpio/fsl_gpio_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/llwu/fsl_llwu_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lptmr/fsl_lptmr_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mpu/fsl_mpu_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/osc/fsl_osc_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pdb/fsl_pdb_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pit/fsl_pit_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/pmc/fsl_pmc_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/port/fsl_port_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rcm/fsl_rcm_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_features.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/wdog/fsl_wdog_hal.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/mbed KSDK readme.txt create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_misc_utilities.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/fsl_os_abstraction_mbed.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_misc_utilities.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/src/fsl_os_abstraction_mbed.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/utilities/sw_timer.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_clock_K64F12.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/MK64F12/fsl_sim_hal_K64F12.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/crc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_FRDM/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PeripheralPins.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/PinNames.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/device.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/mbed_overrides.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_adc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_aips.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_can.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cau.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmp.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmt.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_crc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dac.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dma.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dmamux.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_enet.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ewm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fb.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fmc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftfe.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_gpio.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2c.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2s.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_llwu.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_lptmr.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcg.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mpu.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_nv.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_osc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pdb.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pit.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_port.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rcm.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfsys.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rfvbat.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rtc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sdhc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_sim.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_smc.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_spi.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_uart.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usb.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usbdcd.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_vref.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_wdog.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/fsl_device_registers.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogin_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/analogout_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/gpio_object.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/i2c_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/objects.h create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pinmap.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/port_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/pwmout_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/rtc_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/sleep.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/spi_api.c create mode 100644 targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/us_ticker.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/.serial_api.c.swp create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/PortNames.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PeripheralNames.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/analogin_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/analogout_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/device.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_object.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/objects.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/port_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/pwmout_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/rtc_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/PortNames.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PeripheralNames.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/PinNames.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/TARGET_MAXWSNENV/low_level_init.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/device.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_object.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/i2c_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/objects.h create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/pinmap.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/port_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/pwmout_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/rtc_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/serial_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/sleep.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/spi_api.c create mode 100644 targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/.objects.h.swp create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_licence_agreement.txt create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/PeripheralNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/PortNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_ARCH_BLE/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_ARCH_BLE/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/rtc_api.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_HRM1017/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_Y5_MBUG/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_Y5_MBUG/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DONGLE/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DONGLE/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_RBLAB_BLENANO/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_RBLAB_BLENANO/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_RBLAB_NRF51822/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_RBLAB_NRF51822/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_SEEED_TINY_BLE/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_WALLBOT_BLE/PinNames.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_WALLBOT_BLE/device.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_api.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c create mode 100755 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pinmap.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/port_api.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c create mode 100755 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c create mode 100755 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c create mode 100755 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_config.h create mode 100755 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.c create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.h create mode 100644 targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11U6X/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_ARCH_GPRS/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_ARCH_GPRS/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_ARCH_GPRS/PinNames.h create mode 100755 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_ARCH_GPRS/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_401/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_XADOW_M0/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_XADOW_M0/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PeripheralPins.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_OC_MBUINO/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/README.md create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/reserved_pins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/reserved_pins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC13XX/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/analogout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC15XX/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_ARCH_PRO/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_ARCH_PRO/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_ARCH_PRO/reserved_pins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/reserved_pins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/C027_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/C027_api.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/mbed_overrides.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/reserved_pins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_XBED_LPC1768/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_XBED_LPC1768/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/TARGET_XBED_LPC1768/reserved_pins.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/analogout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/ethernet_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC176X/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/analogout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/ethernet_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC23XX/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/analogout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/ethernet_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC2460/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/analogout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC408X/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4330/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4330/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/TARGET_LPC4337/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/analogout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/port_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/rtc_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC43XX/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/PortNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/analogin_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/gpio_object.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/i2c_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/objects.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/pinmap.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/pwmout_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/serial_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/sleep.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c create mode 100644 targets/hal/TARGET_NXP/TARGET_LPC82X/us_ticker.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernetext_api.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/rtc_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c create mode 100644 targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/PeripheralPins.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/PeripheralPins.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F1/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/PeripheralPins.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F3XX/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/PeripheralPins.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F4XX/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/PeripheralPins.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32F7/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/PeripheralPins.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/rtc_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/gpio_irq_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/pwmout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/serial_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L0/us_ticker.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/PeripheralPins.h create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralPins.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PinNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PortNames.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/device.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/objects.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/analogin_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/gpio_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/gpio_irq_api.c create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/i2c_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/mbed_overrides.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/pinmap.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/port_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/pwmout_api.c create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c create mode 100755 targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c create mode 100644 targets/hal/TARGET_STM/TARGET_STM32L1/us_ticker.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/Modules.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PeripheralPins.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PinNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/PortNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/device_peripherals.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/Modules.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PeripheralPins.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PinNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/PortNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/device_peripherals.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/Modules.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PeripheralPins.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PinNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/PortNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device_peripherals.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/Modules.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PeripheralPins.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PinNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/PortNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device_peripherals.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/Modules.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PeripheralPins.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PinNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/PortNames.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/device_peripherals.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/analogout_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/clocking.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/dma_api_HAL.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/ReadMe_emlib.txt create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_acmp.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_adc.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_aes.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_assert.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_bitband.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_burtc.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_chip.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_cmu.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_common.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dac.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dbg.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_dma.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_gpio.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_i2c.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_idac.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_int.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lcd.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_lesense.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_letimer.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_leuart.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_msc.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_opamp.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_part.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_pcnt.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_prs.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rmu.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_rtc.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_system.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_timer.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_vcmp.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_version.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_wdog.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_acmp.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_adc.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_aes.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_assert.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_burtc.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dac.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dbg.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_dma.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_emu.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_idac.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_int.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lcd.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_lesense.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_letimer.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_leuart.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_mpu.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_msc.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_opamp.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_pcnt.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_prs.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rtc.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_system.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_timer.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_usart.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_vcmp.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_wdog.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/error.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/lp_ticker.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/mbed_overrides.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/objects.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pinmap_function.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/port_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/rtc_api_HAL.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleep.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/sleepmodes.h create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c create mode 100644 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralPins.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PinNames.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/mbed_overrides.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/port_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c create mode 100644 targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..2d72319 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,117 @@ +# +# mbed-2 yotta-compatible build system +# + +# make sure necessary features are enabled: +project(mbed-classic) +enable_language(ASM) + +# override compilation flags: +if(CMAKE_C_COMPILER_ID MATCHES GNU) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=gnu99") +endif() + +# the mbed.a library is built from two sets of source files + include +# directories: +# +# MBED_COMMON_SOURCES: the source files that are the same for all targets, +# these are easily found by globbing: +# +file(GLOB MBED_COMMON_SOURCES "common/*.cpp" "common/*.c") +# +# (always include the hal header directory, too) +set(MBED_COMMON_INCLUDE_DIRS "hal") + +# and MBED_TARGET_SOURCES: these depend on which target we are building for. To +# find these we need to walk the directories in targets/, and wherever we see a +# TARGET_ name, recurse only if matches what we're +# currently building for +macro(mbed_find_target_dirs PARENT_DIRECTORY SOURCES_LIST INCLUDES_LIST) + # append this directory to the search path: + list(APPEND ${INCLUDES_LIST} "${PARENT_DIRECTORY}") + # add all source files in this directory to the sources list: + file(GLOB sources "${PARENT_DIRECTORY}/*.cpp" "${PARENT_DIRECTORY}/*.c" "${PARENT_DIRECTORY}/*.s" "${PARENT_DIRECTORY}/*.S" ) + list(APPEND ${SOURCES_LIST} ${sources}) + + # get a list of all subdirectories that we want to recurse into: + file(GLOB dir_children RELATIVE "${PARENT_DIRECTORY}" "${PARENT_DIRECTORY}/*") + set(matching_subdirs "") + foreach(child ${dir_children}) + if(IS_DIRECTORY "${PARENT_DIRECTORY}/${child}") + # is this directory name a magic one? + if("${child}" MATCHES "^TARGET_") + # target-magic: recurse if the MBED_LEGACY_TARGET_DEFINITIONS **list** + # contains a matching value: + foreach(legacy_magic_def ${MBED_LEGACY_TARGET_DEFINITIONS}) + # we could probably unroll the list into a single regex if + # this is a performance problem: + if("${child}" MATCHES "^TARGET_${legacy_magic_def}$") + list(APPEND matching_subdirs ${child}) + break() + endif() + endforeach() + elseif("${child}" MATCHES "^TOOLCHAIN_") + # toolchain-magic: (recurse if the MBED_LEGACY_TOOLCHAIN matches + # this name) + if("${child}" MATCHES "^TOOLCHAIN_${MBED_LEGACY_TOOLCHAIN}$") + list(APPEND matching_subdirs "${child}") + endif() + else() + # not special: always recurse into this directory + list(APPEND matching_subdirs "${child}") + endif() + endif() + endforeach() + #message("matching_subdirs: ${matching_subdirs}") + + # recurse: + foreach(subdir ${matching_subdirs}) + mbed_find_target_dirs("${PARENT_DIRECTORY}/${subdir}" ${SOURCES_LIST} ${INCLUDES_LIST}) + endforeach() +endmacro() + +set(MBED_TARGET_SOURCES "") +set(MBED_TARGET_INCLUDE_DIRS "") +mbed_find_target_dirs("${CMAKE_CURRENT_SOURCE_DIR}/targets" MBED_TARGET_SOURCES MBED_TARGET_INCLUDE_DIRS) +#message("found target sources: ${MBED_TARGET_SOURCES}") +#message("found target include dirs: ${MBED_TARGET_INCLUDE_DIRS}") + +# unfortunately, for ARMCC, the startup code needs to be provided as an object +# on the command line (not as part of an archive). To do this we override the +# CMake add_executable command. +if(CMAKE_C_COMPILER_ID STREQUAL "ARMCC") + set(MBED_TARGET_STARTUP_CODE_SOURCES "") + foreach(src ${MBED_TARGET_SOURCES}) + if("${src}" MATCHES .*startup_.*\\.[sS]) + LIST(APPEND MBED_TARGET_STARTUP_CODE_SOURCES "${src}") + endif() + endforeach() + add_library(mbed_classic_startupcod OBJECT ${MBED_TARGET_STARTUP_CODE_SOURCES}) + macro (add_executable _name) + _add_executable(${ARGV} $) + endmacro() +endif() + +# we have to append any target-specific include dirs to the global include dirs +# list, so that any indirect includes (e.g. via mbed.h) of files in those +# directories will work: +# (non-target-specific include dirs are listed in extraIncludes in module.json) +foreach(dir ${MBED_TARGET_INCLUDE_DIRS}) + set_property(GLOBAL APPEND PROPERTY YOTTA_GLOBAL_INCLUDE_DIRS ${dir}) +endforeach() + +# finally, we can construct a library using the determined set of include paths +# + source files. Note that the library name must match the name of the yotta +# module (defined in module.json) for this module to link properly with other +# yotta modules. +include_directories(${MBED_COMMON_INCLUDE_DIRS}) +include_directories(${MBED_TARGET_INCLUDE_DIRS}) +add_library(mbed-classic + ${MBED_COMMON_SOURCES} + ${MBED_TARGET_SOURCES} +) +if(CMAKE_COMPILER_IS_GNUCC) + target_link_libraries(mbed-classic + -lnosys + ) +endif() diff --git a/api/AnalogIn.h b/api/AnalogIn.h new file mode 100644 index 0000000..09437a2 --- /dev/null +++ b/api/AnalogIn.h @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ANALOGIN_H +#define MBED_ANALOGIN_H + +#include "platform.h" + +#if DEVICE_ANALOGIN + +#include "analogin_api.h" + +namespace mbed { + +/** An analog input, used for reading the voltage on a pin + * + * Example: + * @code + * // Print messages when the AnalogIn is greater than 50% + * + * #include "mbed.h" + * + * AnalogIn temperature(p20); + * + * int main() { + * while(1) { + * if(temperature > 0.5) { + * printf("Too hot! (%f)", temperature.read()); + * } + * } + * } + * @endcode + */ +class AnalogIn { + +public: + + /** Create an AnalogIn, connected to the specified pin + * + * @param pin AnalogIn pin to connect to + * @param name (optional) A string to identify the object + */ + AnalogIn(PinName pin) { + analogin_init(&_adc, pin); + } + + /** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @returns A floating-point value representing the current input voltage, measured as a percentage + */ + float read() { + return analogin_read(&_adc); + } + + /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF] + * + * @returns + * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value + */ + unsigned short read_u16() { + return analogin_read_u16(&_adc); + } + +#ifdef MBED_OPERATORS + /** An operator shorthand for read() + * + * The float() operator can be used as a shorthand for read() to simplify common code sequences + * + * Example: + * @code + * float x = volume.read(); + * float x = volume; + * + * if(volume.read() > 0.25) { ... } + * if(volume > 0.25) { ... } + * @endcode + */ + operator float() { + return read(); + } +#endif + +protected: + analogin_t _adc; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/AnalogOut.h b/api/AnalogOut.h new file mode 100644 index 0000000..0b879a7 --- /dev/null +++ b/api/AnalogOut.h @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ANALOGOUT_H +#define MBED_ANALOGOUT_H + +#include "platform.h" + +#if DEVICE_ANALOGOUT + +#include "analogout_api.h" + +namespace mbed { + +/** An analog output, used for setting the voltage on a pin + * + * Example: + * @code + * // Make a sawtooth output + * + * #include "mbed.h" + * + * AnalogOut tri(p18); + * int main() { + * while(1) { + * tri = tri + 0.01; + * wait_us(1); + * if(tri == 1) { + * tri = 0; + * } + * } + * } + * @endcode + */ +class AnalogOut { + +public: + + /** Create an AnalogOut connected to the specified pin + * + * @param AnalogOut pin to connect to (18) + */ + AnalogOut(PinName pin) { + analogout_init(&_dac, pin); + } + + /** Set the output voltage, specified as a percentage (float) + * + * @param value A floating-point value representing the output voltage, + * specified as a percentage. The value should lie between + * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%). + * Values outside this range will be saturated to 0.0f or 1.0f. + */ + void write(float value) { + analogout_write(&_dac, value); + } + + /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF] + * + * @param value 16-bit unsigned short representing the output voltage, + * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v) + */ + void write_u16(unsigned short value) { + analogout_write_u16(&_dac, value); + } + + /** Return the current output voltage setting, measured as a percentage (float) + * + * @returns + * A floating-point value representing the current voltage being output on the pin, + * measured as a percentage. The returned value will lie between + * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%). + * + * @note + * This value may not match exactly the value set by a previous write(). + */ + float read() { + return analogout_read(&_dac); + } + +#ifdef MBED_OPERATORS + /** An operator shorthand for write() + */ + AnalogOut& operator= (float percent) { + write(percent); + return *this; + } + + AnalogOut& operator= (AnalogOut& rhs) { + write(rhs.read()); + return *this; + } + + /** An operator shorthand for read() + */ + operator float() { + return read(); + } +#endif + +protected: + dac_t _dac; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/BusIn.h b/api/BusIn.h new file mode 100644 index 0000000..d1c9a9c --- /dev/null +++ b/api/BusIn.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_BUSIN_H +#define MBED_BUSIN_H + +#include "platform.h" +#include "DigitalIn.h" + +namespace mbed { + +/** A digital input bus, used for reading the state of a collection of pins + */ +class BusIn { + +public: + /* Group: Configuration Methods */ + + /** Create an BusIn, connected to the specified pins + * + * @param DigitalIn pin to connect to bus bit (p5-p30, NC) + * + * @note + * It is only required to specify as many pin variables as is required + * for the bus; the rest will default to NC (not connected) + */ + BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC, + PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC, + PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC, + PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC); + + BusIn(PinName pins[16]); + + virtual ~BusIn(); + + /** Read the value of the input bus + * + * @returns + * An integer with each bit corresponding to the value read from the associated DigitalIn pin + */ + int read(); + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone + */ + void mode(PinMode pull); + + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + +#ifdef MBED_OPERATORS + /** A shorthand for read() + */ + operator int(); + + /** Access to particular bit in random-iterator fashion + */ + DigitalIn & operator[] (int index); +#endif + +protected: + DigitalIn* _pin[16]; + + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) + */ + int _nc_mask; + + /* disallow copy constructor and assignment operators */ +private: + BusIn(const BusIn&); + BusIn & operator = (const BusIn&); +}; + +} // namespace mbed + +#endif diff --git a/api/BusInOut.h b/api/BusInOut.h new file mode 100644 index 0000000..54328fb --- /dev/null +++ b/api/BusInOut.h @@ -0,0 +1,117 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_BUSINOUT_H +#define MBED_BUSINOUT_H + +#include "DigitalInOut.h" + +namespace mbed { + +/** A digital input output bus, used for setting the state of a collection of pins + */ +class BusInOut { + +public: + + /** Create an BusInOut, connected to the specified pins + * + * @param p DigitalInOut pin to connect to bus bit p (p5-p30, NC) + * + * @note + * It is only required to specify as many pin variables as is required + * for the bus; the rest will default to NC (not connected) + */ + BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC, + PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC, + PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC, + PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC); + + BusInOut(PinName pins[16]); + + virtual ~BusInOut(); + + /* Group: Access Methods */ + + /** Write the value to the output bus + * + * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin + */ + void write(int value); + + /** Read the value currently output on the bus + * + * @returns + * An integer with each bit corresponding to associated DigitalInOut pin setting + */ + int read(); + + /** Set as an output + */ + void output(); + + /** Set as an input + */ + void input(); + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone + */ + void mode(PinMode pull); + + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + +#ifdef MBED_OPERATORS + /** A shorthand for write() + */ + BusInOut& operator= (int v); + BusInOut& operator= (BusInOut& rhs); + + /** Access to particular bit in random-iterator fashion + */ + DigitalInOut& operator[] (int index); + + /** A shorthand for read() + */ + operator int(); +#endif + +protected: + DigitalInOut* _pin[16]; + + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) + */ + int _nc_mask; + + /* disallow copy constructor and assignment operators */ +private: + BusInOut(const BusInOut&); + BusInOut & operator = (const BusInOut&); +}; + +} // namespace mbed + +#endif diff --git a/api/BusOut.h b/api/BusOut.h new file mode 100644 index 0000000..1c55be0 --- /dev/null +++ b/api/BusOut.h @@ -0,0 +1,101 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_BUSOUT_H +#define MBED_BUSOUT_H + +#include "DigitalOut.h" + +namespace mbed { + +/** A digital output bus, used for setting the state of a collection of pins + */ +class BusOut { + +public: + + /** Create an BusOut, connected to the specified pins + * + * @param p DigitalOut pin to connect to bus bit (p5-p30, NC) + * + * @note + * It is only required to specify as many pin variables as is required + * for the bus; the rest will default to NC (not connected) + */ + BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC, + PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC, + PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC, + PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC); + + BusOut(PinName pins[16]); + + virtual ~BusOut(); + + /** Write the value to the output bus + * + * @param value An integer specifying a bit to write for every corresponding DigitalOut pin + */ + void write(int value); + + /** Read the value currently output on the bus + * + * @returns + * An integer with each bit corresponding to associated DigitalOut pin setting + */ + int read(); + + /** Binary mask of bus pins connected to actual pins (not NC pins) + * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1 + * + * @returns + * Binary mask of connected pins + */ + int mask() { + return _nc_mask; + } + +#ifdef MBED_OPERATORS + /** A shorthand for write() + */ + BusOut& operator= (int v); + BusOut& operator= (BusOut& rhs); + + /** Access to particular bit in random-iterator fashion + */ + DigitalOut& operator[] (int index); + + /** A shorthand for read() + */ + operator int(); +#endif + +protected: + DigitalOut* _pin[16]; + + /** Mask of bus's NC pins + * If bit[n] is set to 1 - pin is connected + * if bit[n] is cleared - pin is not connected (NC) + */ + int _nc_mask; + + /* disallow copy constructor and assignment operators */ +private: + BusOut(const BusOut&); + BusOut & operator = (const BusOut&); +}; + +} // namespace mbed + +#endif diff --git a/api/CAN.h b/api/CAN.h new file mode 100644 index 0000000..db613f6 --- /dev/null +++ b/api/CAN.h @@ -0,0 +1,243 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CAN_H +#define MBED_CAN_H + +#include "platform.h" + +#if DEVICE_CAN + +#include "can_api.h" +#include "can_helper.h" +#include "FunctionPointer.h" + +namespace mbed { + +/** CANMessage class + */ +class CANMessage : public CAN_Message { + +public: + /** Creates empty CAN message. + */ + CANMessage() : CAN_Message() { + len = 8; + type = CANData; + format = CANStandard; + id = 0; + memset(data, 0, 8); + } + + /** Creates CAN message with specific content. + */ + CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) { + len = _len & 0xF; + type = _type; + format = _format; + id = _id; + memcpy(data, _data, _len); + } + + /** Creates CAN remote message. + */ + CANMessage(int _id, CANFormat _format = CANStandard) { + len = 0; + type = CANRemote; + format = _format; + id = _id; + memset(data, 0, 8); + } +}; + +/** A can bus client, used for communicating with can devices + */ +class CAN { + +public: + /** Creates an CAN interface connected to specific pins. + * + * @param rd read from transmitter + * @param td transmit to transmitter + * + * Example: + * @code + * #include "mbed.h" + * + * Ticker ticker; + * DigitalOut led1(LED1); + * DigitalOut led2(LED2); + * CAN can1(p9, p10); + * CAN can2(p30, p29); + * + * char counter = 0; + * + * void send() { + * if(can1.write(CANMessage(1337, &counter, 1))) { + * printf("Message sent: %d\n", counter); + * counter++; + * } + * led1 = !led1; + * } + * + * int main() { + * ticker.attach(&send, 1); + * CANMessage msg; + * while(1) { + * if(can2.read(msg)) { + * printf("Message received: %d\n\n", msg.data[0]); + * led2 = !led2; + * } + * wait(0.2); + * } + * } + * @endcode + */ + CAN(PinName rd, PinName td); + virtual ~CAN(); + + /** Set the frequency of the CAN interface + * + * @param hz The bus frequency in hertz + * + * @returns + * 1 if successful, + * 0 otherwise + */ + int frequency(int hz); + + /** Write a CANMessage to the bus. + * + * @param msg The CANMessage to write. + * + * @returns + * 0 if write failed, + * 1 if write was successful + */ + int write(CANMessage msg); + + /** Read a CANMessage from the bus. + * + * @param msg A CANMessage to read to. + * @param handle message filter handle (0 for any message) + * + * @returns + * 0 if no message arrived, + * 1 if message arrived + */ + int read(CANMessage &msg, int handle = 0); + + /** Reset CAN interface. + * + * To use after error overflow. + */ + void reset(); + + /** Puts or removes the CAN interface into silent monitoring mode + * + * @param silent boolean indicating whether to go into silent mode or not + */ + void monitor(bool silent); + + enum Mode { + Reset = 0, + Normal, + Silent, + LocalTest, + GlobalTest, + SilentTest + }; + + /** Change CAN operation to the specified mode + * + * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest) + * + * @returns + * 0 if mode change failed or unsupported, + * 1 if mode change was successful + */ + int mode(Mode mode); + + /** Filter out incomming messages + * + * @param id the id to filter on + * @param mask the mask applied to the id + * @param format format to filter on (Default CANAny) + * @param handle message filter handle (Optional) + * + * @returns + * 0 if filter change failed or unsupported, + * new filter handle if successful + */ + int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0); + + /** Returns number of read errors to detect read overflow errors. + */ + unsigned char rderror(); + + /** Returns number of write errors to detect write overflow errors. + */ + unsigned char tderror(); + + enum IrqType { + RxIrq = 0, + TxIrq, + EwIrq, + DoIrq, + WuIrq, + EpIrq, + AlIrq, + BeIrq, + IdIrq + }; + + /** Attach a function to call whenever a CAN frame received interrupt is + * generated. + * + * @param fptr A pointer to a void function, or 0 to set as none + * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error) + */ + void attach(void (*fptr)(void), IrqType type=RxIrq); + + /** Attach a member function to call whenever a CAN frame received interrupt + * is generated. + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error) + */ + template + void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { + if((mptr != NULL) && (tptr != NULL)) { + _irq[type].attach(tptr, mptr); + can_irq_set(&_can, (CanIrqType)type, 1); + } + else { + can_irq_set(&_can, (CanIrqType)type, 0); + } + } + + static void _irq_handler(uint32_t id, CanIrqType type); + +protected: + can_t _can; + FunctionPointer _irq[9]; +}; + +} // namespace mbed + +#endif + +#endif // MBED_CAN_H diff --git a/api/CThunk.h b/api/CThunk.h new file mode 100644 index 0000000..96f3331 --- /dev/null +++ b/api/CThunk.h @@ -0,0 +1,202 @@ +/* General C++ Object Thunking class + * + * - allows direct callbacks to non-static C++ class functions + * - keeps track for the corresponding class instance + * - supports an optional context parameter for the called function + * - ideally suited for class object receiving interrupts (NVIC_SetVector) + * + * Copyright (c) 2014-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __CTHUNK_H__ +#define __CTHUNK_H__ + +#define CTHUNK_ADDRESS 1 + +#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__) +#define CTHUNK_VARIABLES volatile uint32_t code[1] +/** +* CTHUNK disassembly for Cortex-M3/M4 (thumb2): +* * ldm.w pc,{r0,r1,r2,pc} +* +* This instruction loads the arguments for the static thunking function to r0-r2, and +* branches to that function by loading its address into PC. +* +* This is safe for both regular calling and interrupt calling, since it only touches scratch registers +* which should be saved by the caller, and are automatically saved as part of the IRQ context switch. +*/ +#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F + +#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) +/* +* CTHUNK disassembly for Cortex M0 (thumb): +* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address +* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1) +* * add r4,pc set up address to load arguments from (immediately following this code block) (2) +* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function +* * blx r3 call static thunk function +* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function +*/ +#define CTHUNK_VARIABLES volatile uint32_t code[3] +#define CTHUNK_ASSIGMENT do { \ + m_thunk.code[0] = 0x2404B51F; \ + m_thunk.code[1] = 0xCC0F447C; \ + m_thunk.code[2] = 0xBD1F4798; \ + } while (0) + +#else +#error "Target is not currently suported." +#endif + +/* IRQ/Exception compatible thunk entry function */ +typedef void (*CThunkEntry)(void); + +template +class CThunk +{ + public: + typedef void (T::*CCallbackSimple)(void); + typedef void (T::*CCallback)(void* context); + + inline CThunk(T *instance) + { + init(instance, NULL, NULL); + } + + inline CThunk(T *instance, CCallback callback) + { + init(instance, callback, NULL); + } + + ~CThunk() { + + } + + inline CThunk(T *instance, CCallbackSimple callback) + { + init(instance, (CCallback)callback, NULL); + } + + inline CThunk(T &instance, CCallback callback) + { + init(instance, callback, NULL); + } + + inline CThunk(T &instance, CCallbackSimple callback) + { + init(instance, (CCallback)callback, NULL); + } + + inline CThunk(T &instance, CCallback callback, void* context) + { + init(instance, callback, context); + } + + inline void callback(CCallback callback) + { + m_callback = callback; + } + + inline void callback(CCallbackSimple callback) + { + m_callback = (CCallback)callback; + } + + inline void context(void* context) + { + m_thunk.context = (uint32_t)context; + } + + inline void context(uint32_t context) + { + m_thunk.context = context; + } + + inline uint32_t entry(void) + { + return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS); + } + + /* get thunk entry point for connecting rhunk to an IRQ table */ + inline operator CThunkEntry(void) + { + return (CThunkEntry)entry(); + } + + /* get thunk entry point for connecting rhunk to an IRQ table */ + inline operator uint32_t(void) + { + return entry(); + } + + /* simple test function */ + inline void call(void) + { + (((CThunkEntry)(entry()))()); + } + + private: + T* m_instance; + volatile CCallback m_callback; + +// TODO: this needs proper fix, to refactor toolchain header file and all its use +// PACKED there is not defined properly for IAR +#if defined (__ICCARM__) + typedef __packed struct + { + CTHUNK_VARIABLES; + volatile uint32_t instance; + volatile uint32_t context; + volatile uint32_t callback; + volatile uint32_t trampoline; + } CThunkTrampoline; +#else + typedef struct + { + CTHUNK_VARIABLES; + volatile uint32_t instance; + volatile uint32_t context; + volatile uint32_t callback; + volatile uint32_t trampoline; + } __attribute__((__packed__)) CThunkTrampoline; +#endif + + static void trampoline(T* instance, void* context, CCallback* callback) + { + if(instance && *callback) { + (static_cast(instance)->**callback)(context); + } + } + + volatile CThunkTrampoline m_thunk; + + inline void init(T *instance, CCallback callback, void* context) + { + /* remember callback - need to add this level of redirection + as pointer size for member functions differs between platforms */ + m_callback = callback; + + /* populate thunking trampoline */ + CTHUNK_ASSIGMENT; + m_thunk.context = (uint32_t)context; + m_thunk.instance = (uint32_t)instance; + m_thunk.callback = (uint32_t)&m_callback; + m_thunk.trampoline = (uint32_t)&trampoline; + + __ISB(); + __DSB(); + } +}; + +#endif/*__CTHUNK_H__*/ diff --git a/api/CallChain.h b/api/CallChain.h new file mode 100644 index 0000000..ebb796a --- /dev/null +++ b/api/CallChain.h @@ -0,0 +1,181 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CALLCHAIN_H +#define MBED_CALLCHAIN_H + +#include "FunctionPointer.h" +#include + +namespace mbed { + +/** Group one or more functions in an instance of a CallChain, then call them in + * sequence using CallChain::call(). Used mostly by the interrupt chaining code, + * but can be used for other purposes. + * + * Example: + * @code + * #include "mbed.h" + * + * CallChain chain; + * + * void first(void) { + * printf("'first' function.\n"); + * } + * + * void second(void) { + * printf("'second' function.\n"); + * } + * + * class Test { + * public: + * void f(void) { + * printf("A::f (class member).\n"); + * } + * }; + * + * int main() { + * Test test; + * + * chain.add(second); + * chain.add_front(first); + * chain.add(&test, &Test::f); + * chain.call(); + * } + * @endcode + */ + +typedef FunctionPointer* pFunctionPointer_t; + +class CallChain { +public: + /** Create an empty chain + * + * @param size (optional) Initial size of the chain + */ + CallChain(int size = 4); + virtual ~CallChain(); + + /** Add a function at the end of the chain + * + * @param function A pointer to a void function + * + * @returns + * The function object created for 'function' + */ + pFunctionPointer_t add(void (*function)(void)); + + /** Add a function at the end of the chain + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + * + * @returns + * The function object created for 'tptr' and 'mptr' + */ + template + pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) { + return common_add(new FunctionPointer(tptr, mptr)); + } + + /** Add a function at the beginning of the chain + * + * @param function A pointer to a void function + * + * @returns + * The function object created for 'function' + */ + pFunctionPointer_t add_front(void (*function)(void)); + + /** Add a function at the beginning of the chain + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + * + * @returns + * The function object created for 'tptr' and 'mptr' + */ + template + pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) { + return common_add_front(new FunctionPointer(tptr, mptr)); + } + + /** Get the number of functions in the chain + */ + int size() const; + + /** Get a function object from the chain + * + * @param i function object index + * + * @returns + * The function object at position 'i' in the chain + */ + pFunctionPointer_t get(int i) const; + + /** Look for a function object in the call chain + * + * @param f the function object to search + * + * @returns + * The index of the function object if found, -1 otherwise. + */ + int find(pFunctionPointer_t f) const; + + /** Clear the call chain (remove all functions in the chain). + */ + void clear(); + + /** Remove a function object from the chain + * + * @arg f the function object to remove + * + * @returns + * true if the function object was found and removed, false otherwise. + */ + bool remove(pFunctionPointer_t f); + + /** Call all the functions in the chain in sequence + */ + void call(); + +#ifdef MBED_OPERATORS + void operator ()(void) { + call(); + } + pFunctionPointer_t operator [](int i) const { + return get(i); + } +#endif + +private: + void _check_size(); + pFunctionPointer_t common_add(pFunctionPointer_t pf); + pFunctionPointer_t common_add_front(pFunctionPointer_t pf); + + pFunctionPointer_t* _chain; + int _size; + int _elements; + + /* disallow copy constructor and assignment operators */ +private: + CallChain(const CallChain&); + CallChain & operator = (const CallChain&); +}; + +} // namespace mbed + +#endif + diff --git a/api/CircularBuffer.h b/api/CircularBuffer.h new file mode 100644 index 0000000..e9f3f1c --- /dev/null +++ b/api/CircularBuffer.h @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CIRCULARBUFFER_H +#define MBED_CIRCULARBUFFER_H + +namespace mbed { + +/** Templated Circular buffer class + */ +template +class CircularBuffer { +public: + CircularBuffer() : _head(0), _tail(0), _full(false) { + } + + ~CircularBuffer() { + } + + /** Push the transaction to the buffer. This overwrites the buffer if it's + * full + * + * @param data Data to be pushed to the buffer + */ + void push(const T& data) { + if (full()) { + _tail++; + _tail %= BufferSize; + } + _pool[_head++] = data; + _head %= BufferSize; + if (_head == _tail) { + _full = true; + } + } + + /** Pop the transaction from the buffer + * + * @param data Data to be pushed to the buffer + * @return True if the buffer is not empty and data contains a transaction, false otherwise + */ + bool pop(T& data) { + if (!empty()) { + data = _pool[_tail++]; + _tail %= BufferSize; + _full = false; + return true; + } + return false; + } + + /** Check if the buffer is empty + * + * @return True if the buffer is empty, false if not + */ + bool empty() { + return (_head == _tail) && !_full; + } + + /** Check if the buffer is full + * + * @return True if the buffer is full, false if not + */ + bool full() { + return _full; + } + + /** Reset the buffer + * + */ + void reset() { + _head = 0; + _tail = 0; + _full = false; + } + +private: + T _pool[BufferSize]; + volatile CounterType _head; + volatile CounterType _tail; + volatile bool _full; +}; + +} + +#endif diff --git a/api/DigitalIn.h b/api/DigitalIn.h new file mode 100644 index 0000000..b089de9 --- /dev/null +++ b/api/DigitalIn.h @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DIGITALIN_H +#define MBED_DIGITALIN_H + +#include "platform.h" + +#include "gpio_api.h" + +namespace mbed { + +/** A digital input, used for reading the state of a pin + * + * Example: + * @code + * // Flash an LED while a DigitalIn is true + * + * #include "mbed.h" + * + * DigitalIn enable(p5); + * DigitalOut led(LED1); + * + * int main() { + * while(1) { + * if(enable) { + * led = !led; + * } + * wait(0.25); + * } + * } + * @endcode + */ +class DigitalIn { + +public: + /** Create a DigitalIn connected to the specified pin + * + * @param pin DigitalIn pin to connect to + */ + DigitalIn(PinName pin) : gpio() { + gpio_init_in(&gpio, pin); + } + + /** Create a DigitalIn connected to the specified pin + * + * @param pin DigitalIn pin to connect to + * @param mode the initial mode of the pin + */ + DigitalIn(PinName pin, PinMode mode) : gpio() { + gpio_init_in_ex(&gpio, pin, mode); + } + /** Read the input, represented as 0 or 1 (int) + * + * @returns + * An integer representing the state of the input pin, + * 0 for logical 0, 1 for logical 1 + */ + int read() { + return gpio_read(&gpio); + } + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone, OpenDrain + */ + void mode(PinMode pull) { + gpio_mode(&gpio, pull); + } + + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + +#ifdef MBED_OPERATORS + /** An operator shorthand for read() + */ + operator int() { + return read(); + } +#endif + +protected: + gpio_t gpio; +}; + +} // namespace mbed + +#endif diff --git a/api/DigitalInOut.h b/api/DigitalInOut.h new file mode 100644 index 0000000..e30be0e --- /dev/null +++ b/api/DigitalInOut.h @@ -0,0 +1,124 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DIGITALINOUT_H +#define MBED_DIGITALINOUT_H + +#include "platform.h" + +#include "gpio_api.h" + +namespace mbed { + +/** A digital input/output, used for setting or reading a bi-directional pin + */ +class DigitalInOut { + +public: + /** Create a DigitalInOut connected to the specified pin + * + * @param pin DigitalInOut pin to connect to + */ + DigitalInOut(PinName pin) : gpio() { + gpio_init_in(&gpio, pin); + } + + /** Create a DigitalInOut connected to the specified pin + * + * @param pin DigitalInOut pin to connect to + * @param direction the initial direction of the pin + * @param mode the initial mode of the pin + * @param value the initial value of the pin if is an output + */ + DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() { + gpio_init_inout(&gpio, pin, direction, mode, value); + } + + /** Set the output, specified as 0 or 1 (int) + * + * @param value An integer specifying the pin output value, + * 0 for logical 0, 1 (or any other non-zero value) for logical 1 + */ + void write(int value) { + gpio_write(&gpio, value); + } + + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * an integer representing the output setting of the pin if it is an output, + * or read the input if set as an input + */ + int read() { + return gpio_read(&gpio); + } + + /** Set as an output + */ + void output() { + gpio_dir(&gpio, PIN_OUTPUT); + } + + /** Set as an input + */ + void input() { + gpio_dir(&gpio, PIN_INPUT); + } + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone, OpenDrain + */ + void mode(PinMode pull) { + gpio_mode(&gpio, pull); + } + + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + +#ifdef MBED_OPERATORS + /** A shorthand for write() + */ + DigitalInOut& operator= (int value) { + write(value); + return *this; + } + + DigitalInOut& operator= (DigitalInOut& rhs) { + write(rhs.read()); + return *this; + } + + /** A shorthand for read() + */ + operator int() { + return read(); + } +#endif + +protected: + gpio_t gpio; +}; + +} // namespace mbed + +#endif diff --git a/api/DigitalOut.h b/api/DigitalOut.h new file mode 100644 index 0000000..0d66f90 --- /dev/null +++ b/api/DigitalOut.h @@ -0,0 +1,116 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DIGITALOUT_H +#define MBED_DIGITALOUT_H + +#include "platform.h" +#include "gpio_api.h" + +namespace mbed { + +/** A digital output, used for setting the state of a pin + * + * Example: + * @code + * // Toggle a LED + * #include "mbed.h" + * + * DigitalOut led(LED1); + * + * int main() { + * while(1) { + * led = !led; + * wait(0.2); + * } + * } + * @endcode + */ +class DigitalOut { + +public: + /** Create a DigitalOut connected to the specified pin + * + * @param pin DigitalOut pin to connect to + */ + DigitalOut(PinName pin) : gpio() { + gpio_init_out(&gpio, pin); + } + + /** Create a DigitalOut connected to the specified pin + * + * @param pin DigitalOut pin to connect to + * @param value the initial pin value + */ + DigitalOut(PinName pin, int value) : gpio() { + gpio_init_out_ex(&gpio, pin, value); + } + + /** Set the output, specified as 0 or 1 (int) + * + * @param value An integer specifying the pin output value, + * 0 for logical 0, 1 (or any other non-zero value) for logical 1 + */ + void write(int value) { + gpio_write(&gpio, value); + } + + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * an integer representing the output setting of the pin, + * 0 for logical 0, 1 for logical 1 + */ + int read() { + return gpio_read(&gpio); + } + + /** Return the output setting, represented as 0 or 1 (int) + * + * @returns + * Non zero value if pin is connected to uc GPIO + * 0 if gpio object was initialized with NC + */ + int is_connected() { + return gpio_is_connected(&gpio); + } + +#ifdef MBED_OPERATORS + /** A shorthand for write() + */ + DigitalOut& operator= (int value) { + write(value); + return *this; + } + + DigitalOut& operator= (DigitalOut& rhs) { + write(rhs.read()); + return *this; + } + + /** A shorthand for read() + */ + operator int() { + return read(); + } +#endif + +protected: + gpio_t gpio; +}; + +} // namespace mbed + +#endif diff --git a/api/DirHandle.h b/api/DirHandle.h new file mode 100644 index 0000000..329f4d1 --- /dev/null +++ b/api/DirHandle.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DIRHANDLE_H +#define MBED_DIRHANDLE_H + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +# define NAME_MAX 255 +typedef int mode_t; + +#else +# include +#endif + +#include "FileHandle.h" + +struct dirent { + char d_name[NAME_MAX+1]; +}; + +namespace mbed { + +/** Represents a directory stream. Objects of this type are returned + * by a FileSystemLike's opendir method. Implementations must define + * at least closedir, readdir and rewinddir. + * + * If a FileSystemLike class defines the opendir method, then the + * directories of an object of that type can be accessed by + * DIR *d = opendir("/example/directory") (or opendir("/example") + * to open the root of the filesystem), and then using readdir(d) etc. + * + * The root directory is considered to contain all FileLike and + * FileSystemLike objects, so the DIR* returned by opendir("/") will + * reflect this. + */ +class DirHandle { + +public: + /** Closes the directory. + * + * @returns + * 0 on success, + * -1 on error. + */ + virtual int closedir()=0; + + /** Return the directory entry at the current position, and + * advances the position to the next entry. + * + * @returns + * A pointer to a dirent structure representing the + * directory entry at the current position, or NULL on reaching + * end of directory or error. + */ + virtual struct dirent *readdir()=0; + + /** Resets the position to the beginning of the directory. + */ + virtual void rewinddir()=0; + + /** Returns the current position of the DirHandle. + * + * @returns + * the current position, + * -1 on error. + */ + virtual off_t telldir() { return -1; } + + /** Sets the position of the DirHandle. + * + * @param location The location to seek to. Must be a value returned by telldir. + */ + virtual void seekdir(off_t location) { } + + virtual ~DirHandle() {} +}; + +} // namespace mbed + +typedef mbed::DirHandle DIR; + +extern "C" { + DIR *opendir(const char*); + struct dirent *readdir(DIR *); + int closedir(DIR*); + void rewinddir(DIR*); + long telldir(DIR*); + void seekdir(DIR*, long); + int mkdir(const char *name, mode_t n); +}; + +#endif /* MBED_DIRHANDLE_H */ diff --git a/api/Ethernet.h b/api/Ethernet.h new file mode 100644 index 0000000..d0e59a5 --- /dev/null +++ b/api/Ethernet.h @@ -0,0 +1,170 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ETHERNET_H +#define MBED_ETHERNET_H + +#include "platform.h" + +#if DEVICE_ETHERNET + +namespace mbed { + +/** An ethernet interface, to use with the ethernet pins. + * + * Example: + * @code + * // Read destination and source from every ethernet packet + * + * #include "mbed.h" + * + * Ethernet eth; + * + * int main() { + * char buf[0x600]; + * + * while(1) { + * int size = eth.receive(); + * if(size > 0) { + * eth.read(buf, size); + * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n", + * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n", + * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]); + * } + * + * wait(1); + * } + * } + * @endcode + */ +class Ethernet { + +public: + + /** Initialise the ethernet interface. + */ + Ethernet(); + + /** Powers the hardware down. + */ + virtual ~Ethernet(); + + enum Mode { + AutoNegotiate, + HalfDuplex10, + FullDuplex10, + HalfDuplex100, + FullDuplex100 + }; + + /** Writes into an outgoing ethernet packet. + * + * It will append size bytes of data to the previously written bytes. + * + * @param data An array to write. + * @param size The size of data. + * + * @returns + * The number of written bytes. + */ + int write(const char *data, int size); + + /** Send an outgoing ethernet packet. + * + * After filling in the data in an ethernet packet it must be send. + * Send will provide a new packet to write to. + * + * @returns + * 0 if the sending was failed, + * or the size of the packet successfully sent. + */ + int send(); + + /** Recevies an arrived ethernet packet. + * + * Receiving an ethernet packet will drop the last received ethernet packet + * and make a new ethernet packet ready to read. + * If no ethernet packet is arrived it will return 0. + * + * @returns + * 0 if no ethernet packet is arrived, + * or the size of the arrived packet. + */ + int receive(); + + /** Read from an recevied ethernet packet. + * + * After receive returnd a number bigger than 0it is + * possible to read bytes from this packet. + * Read will write up to size bytes into data. + * + * It is possible to use read multible times. + * Each time read will start reading after the last read byte before. + * + * @returns + * The number of byte read. + */ + int read(char *data, int size); + + /** Gives the ethernet address of the mbed. + * + * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in. + */ + void address(char *mac); + + /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up. + * + * @returns + * 0 if no ethernet link is pressent, + * 1 if an ethernet link is pressent. + * + * Example: + * @code + * // Using the Ethernet link function + * #include "mbed.h" + * + * Ethernet eth; + * + * int main() { + * wait(1); // Needed after startup. + * if (eth.link()) { + * printf("online\n"); + * } else { + * printf("offline\n"); + * } + * } + * @endcode + */ + int link(); + + /** Sets the speed and duplex parameters of an ethernet link + * + * - AutoNegotiate Auto negotiate speed and duplex + * - HalfDuplex10 10 Mbit, half duplex + * - FullDuplex10 10 Mbit, full duplex + * - HalfDuplex100 100 Mbit, half duplex + * - FullDuplex100 100 Mbit, full duplex + * + * @param mode the speed and duplex mode to set the link to: + */ + void set_link(Mode mode); +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/FileBase.h b/api/FileBase.h new file mode 100644 index 0000000..88f8784 --- /dev/null +++ b/api/FileBase.h @@ -0,0 +1,80 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_FILEBASE_H +#define MBED_FILEBASE_H + +typedef int FILEHANDLE; + +#include + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +# define O_RDONLY 0 +# define O_WRONLY 1 +# define O_RDWR 2 +# define O_CREAT 0x0200 +# define O_TRUNC 0x0400 +# define O_APPEND 0x0008 + +# define NAME_MAX 255 + +typedef int mode_t; +typedef int ssize_t; +typedef long off_t; + +#else +# include +# include +# include +#endif + +#include "platform.h" + +namespace mbed { + +typedef enum { + FilePathType, + FileSystemPathType +} PathType; + +class FileBase { +public: + FileBase(const char *name, PathType t); + + virtual ~FileBase(); + + const char* getName(void); + PathType getPathType(void); + + static FileBase *lookup(const char *name, unsigned int len); + + static FileBase *get(int n); + +protected: + static FileBase *_head; + + FileBase *_next; + const char *_name; + PathType _path_type; + + /* disallow copy constructor and assignment operators */ +private: + FileBase(const FileBase&); + FileBase & operator = (const FileBase&); +}; + +} // namespace mbed + +#endif diff --git a/api/FileHandle.h b/api/FileHandle.h new file mode 100644 index 0000000..0a98a82 --- /dev/null +++ b/api/FileHandle.h @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_FILEHANDLE_H +#define MBED_FILEHANDLE_H + +typedef int FILEHANDLE; + +#include + +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef int ssize_t; +typedef long off_t; + +#else +# include +#endif + +namespace mbed { + +/** An OO equivalent of the internal FILEHANDLE variable + * and associated _sys_* functions. + * + * FileHandle is an abstract class, needing at least sys_write and + * sys_read to be implmented for a simple interactive device. + * + * No one ever directly tals to/instanciates a FileHandle - it gets + * created by FileSystem, and wrapped up by stdio. + */ +class FileHandle { + +public: + /** Write the contents of a buffer to the file + * + * @param buffer the buffer to write from + * @param length the number of characters to write + * + * @returns + * The number of characters written (possibly 0) on success, -1 on error. + */ + virtual ssize_t write(const void* buffer, size_t length) = 0; + + /** Close the file + * + * @returns + * Zero on success, -1 on error. + */ + virtual int close() = 0; + + /** Function read + * Reads the contents of the file into a buffer + * + * @param buffer the buffer to read in to + * @param length the number of characters to read + * + * @returns + * The number of characters read (zero at end of file) on success, -1 on error. + */ + virtual ssize_t read(void* buffer, size_t length) = 0; + + /** Check if the handle is for a interactive terminal device. + * If so, line buffered behaviour is used by default + * + * @returns + * 1 if it is a terminal, + * 0 otherwise + */ + virtual int isatty() = 0; + + /** Move the file position to a given offset from a given location. + * + * @param offset The offset from whence to move to + * @param whence SEEK_SET for the start of the file, SEEK_CUR for the + * current file position, or SEEK_END for the end of the file. + * + * @returns + * new file position on success, + * -1 on failure or unsupported + */ + virtual off_t lseek(off_t offset, int whence) = 0; + + /** Flush any buffers associated with the FileHandle, ensuring it + * is up to date on disk + * + * @returns + * 0 on success or un-needed, + * -1 on error + */ + virtual int fsync() = 0; + + virtual off_t flen() { + /* remember our current position */ + off_t pos = lseek(0, SEEK_CUR); + if(pos == -1) return -1; + /* seek to the end to get the file length */ + off_t res = lseek(0, SEEK_END); + /* return to our old position */ + lseek(pos, SEEK_SET); + return res; + } + + virtual ~FileHandle(); +}; + +} // namespace mbed + +#endif diff --git a/api/FileLike.h b/api/FileLike.h new file mode 100644 index 0000000..666575c --- /dev/null +++ b/api/FileLike.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_FILELIKE_H +#define MBED_FILELIKE_H + +#include "FileBase.h" +#include "FileHandle.h" + +namespace mbed { + +/* Class FileLike + * A file-like object is one that can be opened with fopen by + * fopen("/name", mode). It is intersection of the classes Base and + * FileHandle. + */ +class FileLike : public FileHandle, public FileBase { + +public: + /* Constructor FileLike + * + * Variables + * name - The name to use to open the file. + */ + FileLike(const char *name); + + virtual ~FileLike(); +}; + +} // namespace mbed + +#endif diff --git a/api/FilePath.h b/api/FilePath.h new file mode 100644 index 0000000..3de1205 --- /dev/null +++ b/api/FilePath.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_FILEPATH_H +#define MBED_FILEPATH_H + +#include "platform.h" + +#include "FileSystemLike.h" +#include "FileLike.h" + +namespace mbed { + +class FilePath { +public: + FilePath(const char* file_path); + + const char* fileName(void); + + bool isFileSystem(void); + FileSystemLike* fileSystem(void); + + bool isFile(void); + FileLike* file(void); + bool exists(void); + +private: + const char* file_name; + FileBase* fb; +}; + +} // namespace mbed + +#endif diff --git a/api/FileSystemLike.h b/api/FileSystemLike.h new file mode 100644 index 0000000..6680c4c --- /dev/null +++ b/api/FileSystemLike.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_FILESYSTEMLIKE_H +#define MBED_FILESYSTEMLIKE_H + +#include "platform.h" + +#include "FileBase.h" +#include "FileHandle.h" +#include "DirHandle.h" + +namespace mbed { + +/** A filesystem-like object is one that can be used to open files + * though it by fopen("/name/filename", mode) + * + * Implementations must define at least open (the default definitions + * of the rest of the functions just return error values). + */ +class FileSystemLike : public FileBase { + +public: + /** FileSystemLike constructor + * + * @param name The name to use for the filesystem. + */ + FileSystemLike(const char *name); + + virtual ~FileSystemLike(); + + static DirHandle *opendir(); + friend class BaseDirHandle; + + /** Opens a file from the filesystem + * + * @param filename The name of the file to open. + * @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with + * zero or more of O_CREAT, O_TRUNC, or O_APPEND. + * + * @returns + * A pointer to a FileHandle object representing the + * file on success, or NULL on failure. + */ + virtual FileHandle *open(const char *filename, int flags) = 0; + + /** Remove a file from the filesystem. + * + * @param filename the name of the file to remove. + * @param returns 0 on success, -1 on failure. + */ + virtual int remove(const char *filename) { return -1; }; + + /** Rename a file in the filesystem. + * + * @param oldname the name of the file to rename. + * @param newname the name to rename it to. + * + * @returns + * 0 on success, + * -1 on failure. + */ + virtual int rename(const char *oldname, const char *newname) { return -1; }; + + /** Opens a directory in the filesystem and returns a DirHandle + * representing the directory stream. + * + * @param name The name of the directory to open. + * + * @returns + * A DirHandle representing the directory stream, or + * NULL on failure. + */ + virtual DirHandle *opendir(const char *name) { return NULL; }; + + /** Creates a directory in the filesystem. + * + * @param name The name of the directory to create. + * @param mode The permissions to create the directory with. + * + * @returns + * 0 on success, + * -1 on failure. + */ + virtual int mkdir(const char *name, mode_t mode) { return -1; } + + // TODO other filesystem functions (mkdir, rm, rn, ls etc) +}; + +} // namespace mbed + +#endif diff --git a/api/FunctionPointer.h b/api/FunctionPointer.h new file mode 100644 index 0000000..2d49ba0 --- /dev/null +++ b/api/FunctionPointer.h @@ -0,0 +1,202 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_FUNCTIONPOINTER_H +#define MBED_FUNCTIONPOINTER_H + +#include +#include + +namespace mbed { + +/* If we had variaditic templates, this wouldn't be a problem, but until C++11 is enabled, we are stuck with multiple classes... */ + +/** A class for storing and calling a pointer to a static or member function + */ +template +class FunctionPointerArg1{ +public: + /** Create a FunctionPointer, attaching a static function + * + * @param function The static function to attach (default is none) + */ + FunctionPointerArg1(R (*function)(A1) = 0) { + attach(function); + } + + /** Create a FunctionPointer, attaching a member function + * + * @param object The object pointer to invoke the member function on (i.e. the this pointer) + * @param function The address of the member function to attach + */ + template + FunctionPointerArg1(T *object, R (T::*member)(A1)) { + attach(object, member); + } + + /** Attach a static function + * + * @param function The static function to attach (default is none) + */ + void attach(R (*function)(A1)) { + _p.function = function; + _membercaller = 0; + } + + /** Attach a member function + * + * @param object The object pointer to invoke the member function on (i.e. the this pointer) + * @param function The address of the member function to attach + */ + template + void attach(T *object, R (T::*member)(A1)) { + _p.object = static_cast(object); + *reinterpret_cast(_member) = member; + _membercaller = &FunctionPointerArg1::membercaller; + } + + /** Call the attached static or member function + */ + R call(A1 a) { + if (_membercaller == 0 && _p.function) { + return _p.function(a); + } else if (_membercaller && _p.object) { + return _membercaller(_p.object, _member, a); + } + return (R)0; + } + + /** Get registered static function + */ + R(*get_function(A1))() { + return _membercaller ? (R(*)(A1))0 : (R(*)(A1))_p.function; + } + +#ifdef MBED_OPERATORS + R operator ()(A1 a) { + return call(a); + } + operator bool(void) const { + return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL; + } +#endif +private: + template + static R membercaller(void *object, uintptr_t *member, A1 a) { + T* o = static_cast(object); + R (T::**m)(A1) = reinterpret_cast(member); + return (o->**m)(a); + } + + union { + R (*function)(A1); // static function pointer + void *object; // object this pointer + } _p; + uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller + R (*_membercaller)(void*, uintptr_t*, A1); // registered membercaller function to convert back and call _m.member on _object +}; + +/** A class for storing and calling a pointer to a static or member function (R ()(void)) + */ +template +class FunctionPointerArg1{ +public: + /** Create a FunctionPointer, attaching a static function + * + * @param function The static function to attach (default is none) + */ + FunctionPointerArg1(R (*function)(void) = 0) { + attach(function); + } + + /** Create a FunctionPointer, attaching a member function + * + * @param object The object pointer to invoke the member function on (i.e. the this pointer) + * @param function The address of the void member function to attach + */ + template + FunctionPointerArg1(T *object, R (T::*member)(void)) { + attach(object, member); + } + + /** Attach a static function + * + * @param function The void static function to attach (default is none) + */ + void attach(R (*function)(void)) { + _p.function = function; + _membercaller = 0; + } + + /** Attach a member function + * + * @param object The object pointer to invoke the member function on (i.e. the this pointer) + * @param function The address of the void member function to attach + */ + template + void attach(T *object, R (T::*member)(void)) { + _p.object = static_cast(object); + *reinterpret_cast(_member) = member; + _membercaller = &FunctionPointerArg1::membercaller; + } + + /** Call the attached static or member function + */ + R call(){ + if (_membercaller == 0 && _p.function) { + return _p.function(); + } else if (_membercaller && _p.object) { + return _membercaller(_p.object, _member); + } + return (R)0; + } + + /** Get registered static function + */ + R(*get_function())() { + return _membercaller ? (R(*)())0 : (R(*)())_p.function; + } + +#ifdef MBED_OPERATORS + R operator ()(void) { + return call(); + } + operator bool(void) const { + return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL; + } +#endif + +private: + template + static R membercaller(void *object, uintptr_t *member) { + T* o = static_cast(object); + R (T::**m)(void) = reinterpret_cast(member); + return (o->**m)(); + } + + union { + R (*function)(void); // static function pointer + void *object; // object this pointer + } _p; + uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller + R (*_membercaller)(void*, uintptr_t*); // registered membercaller function to convert back and call _m.member on _object +}; + +typedef FunctionPointerArg1 FunctionPointer; +typedef FunctionPointerArg1 event_callback_t; + +} // namespace mbed + +#endif diff --git a/api/I2C.h b/api/I2C.h new file mode 100644 index 0000000..3097fb9 --- /dev/null +++ b/api/I2C.h @@ -0,0 +1,176 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_I2C_H +#define MBED_I2C_H + +#include "platform.h" + +#if DEVICE_I2C + +#include "i2c_api.h" + +#if DEVICE_I2C_ASYNCH +#include "CThunk.h" +#include "dma_api.h" +#include "FunctionPointer.h" +#endif + +namespace mbed { + +/** An I2C Master, used for communicating with I2C slave devices + * + * Example: + * @code + * // Read from I2C slave at address 0x62 + * + * #include "mbed.h" + * + * I2C i2c(p28, p27); + * + * int main() { + * int address = 0x62; + * char data[2]; + * i2c.read(address, data, 2); + * } + * @endcode + */ +class I2C { + +public: + enum RxStatus { + NoData, + MasterGeneralCall, + MasterWrite, + MasterRead + }; + + enum Acknowledge { + NoACK = 0, + ACK = 1 + }; + + /** Create an I2C Master interface, connected to the specified pins + * + * @param sda I2C data line pin + * @param scl I2C clock line pin + */ + I2C(PinName sda, PinName scl); + + /** Set the frequency of the I2C interface + * + * @param hz The bus frequency in hertz + */ + void frequency(int hz); + + /** Read from an I2C slave + * + * Performs a complete read transaction. The bottom bit of + * the address is forced to 1 to indicate a read. + * + * @param address 8-bit I2C slave address [ addr | 1 ] + * @param data Pointer to the byte-array to read data in to + * @param length Number of bytes to read + * @param repeated Repeated start, true - don't send stop at end + * + * @returns + * 0 on success (ack), + * non-0 on failure (nack) + */ + int read(int address, char *data, int length, bool repeated = false); + + /** Read a single byte from the I2C bus + * + * @param ack indicates if the byte is to be acknowledged (1 = acknowledge) + * + * @returns + * the byte read + */ + int read(int ack); + + /** Write to an I2C slave + * + * Performs a complete write transaction. The bottom bit of + * the address is forced to 0 to indicate a write. + * + * @param address 8-bit I2C slave address [ addr | 0 ] + * @param data Pointer to the byte-array data to send + * @param length Number of bytes to send + * @param repeated Repeated start, true - do not send stop at end + * + * @returns + * 0 on success (ack), + * non-0 on failure (nack) + */ + int write(int address, const char *data, int length, bool repeated = false); + + /** Write single byte out on the I2C bus + * + * @param data data to write out on bus + * + * @returns + * '1' if an ACK was received, + * '0' otherwise + */ + int write(int data); + + /** Creates a start condition on the I2C bus + */ + + void start(void); + + /** Creates a stop condition on the I2C bus + */ + void stop(void); + +#if DEVICE_I2C_ASYNCH + + /** Start non-blocking I2C transfer. + * + * @param address 8/10 bit I2c slave address + * @param tx_buffer The TX buffer with data to be transfered + * @param tx_length The length of TX buffer in bytes + * @param rx_buffer The RX buffer which is used for received data + * @param rx_length The length of RX buffer in bytes + * @param event The logical OR of events to modify + * @param callback The event callback function + * @param repeated Repeated start, true - do not send stop at end + * @return Zero if the transfer has started, or -1 if I2C peripheral is busy + */ + int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false); + + /** Abort the on-going I2C transfer + */ + void abort_transfer(); +protected: + void irq_handler_asynch(void); + event_callback_t _callback; + CThunk _irq; + DMAUsage _usage; +#endif + +protected: + void aquire(); + + i2c_t _i2c; + static I2C *_owner; + int _hz; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/I2CSlave.h b/api/I2CSlave.h new file mode 100644 index 0000000..738faea --- /dev/null +++ b/api/I2CSlave.h @@ -0,0 +1,154 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_I2C_SLAVE_H +#define MBED_I2C_SLAVE_H + +#include "platform.h" + +#if DEVICE_I2CSLAVE + +#include "i2c_api.h" + +namespace mbed { + +/** An I2C Slave, used for communicating with an I2C Master device + * + * Example: + * @code + * // Simple I2C responder + * #include + * + * I2CSlave slave(p9, p10); + * + * int main() { + * char buf[10]; + * char msg[] = "Slave!"; + * + * slave.address(0xA0); + * while (1) { + * int i = slave.receive(); + * switch (i) { + * case I2CSlave::ReadAddressed: + * slave.write(msg, strlen(msg) + 1); // Includes null char + * break; + * case I2CSlave::WriteGeneral: + * slave.read(buf, 10); + * printf("Read G: %s\n", buf); + * break; + * case I2CSlave::WriteAddressed: + * slave.read(buf, 10); + * printf("Read A: %s\n", buf); + * break; + * } + * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer + * } + * } + * @endcode + */ +class I2CSlave { + +public: + enum RxStatus { + NoData = 0, + ReadAddressed = 1, + WriteGeneral = 2, + WriteAddressed = 3 + }; + + /** Create an I2C Slave interface, connected to the specified pins. + * + * @param sda I2C data line pin + * @param scl I2C clock line pin + */ + I2CSlave(PinName sda, PinName scl); + + /** Set the frequency of the I2C interface + * + * @param hz The bus frequency in hertz + */ + void frequency(int hz); + + /** Checks to see if this I2C Slave has been addressed. + * + * @returns + * A status indicating if the device has been addressed, and how + * - NoData - the slave has not been addressed + * - ReadAddressed - the master has requested a read from this slave + * - WriteAddressed - the master is writing to this slave + * - WriteGeneral - the master is writing to all slave + */ + int receive(void); + + /** Read from an I2C master. + * + * @param data pointer to the byte array to read data in to + * @param length maximum number of bytes to read + * + * @returns + * 0 on success, + * non-0 otherwise + */ + int read(char *data, int length); + + /** Read a single byte from an I2C master. + * + * @returns + * the byte read + */ + int read(void); + + /** Write to an I2C master. + * + * @param data pointer to the byte array to be transmitted + * @param length the number of bytes to transmite + * + * @returns + * 0 on success, + * non-0 otherwise + */ + int write(const char *data, int length); + + /** Write a single byte to an I2C master. + * + * @data the byte to write + * + * @returns + * '1' if an ACK was received, + * '0' otherwise + */ + int write(int data); + + /** Sets the I2C slave address. + * + * @param address The address to set for the slave (ignoring the least + * signifcant bit). If set to 0, the slave will only respond to the + * general call address. + */ + void address(int address); + + /** Reset the I2C slave back into the known ready receiving state. + */ + void stop(void); + +protected: + i2c_t _i2c; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/InterruptIn.h b/api/InterruptIn.h new file mode 100644 index 0000000..88bc430 --- /dev/null +++ b/api/InterruptIn.h @@ -0,0 +1,135 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_INTERRUPTIN_H +#define MBED_INTERRUPTIN_H + +#include "platform.h" + +#if DEVICE_INTERRUPTIN + +#include "gpio_api.h" +#include "gpio_irq_api.h" +#include "FunctionPointer.h" + +namespace mbed { + +/** A digital interrupt input, used to call a function on a rising or falling edge + * + * Example: + * @code + * // Flash an LED while waiting for events + * + * #include "mbed.h" + * + * InterruptIn event(p16); + * DigitalOut led(LED1); + * + * void trigger() { + * printf("triggered!\n"); + * } + * + * int main() { + * event.rise(&trigger); + * while(1) { + * led = !led; + * wait(0.25); + * } + * } + * @endcode + */ +class InterruptIn { + +public: + + /** Create an InterruptIn connected to the specified pin + * + * @param pin InterruptIn pin to connect to + * @param name (optional) A string to identify the object + */ + InterruptIn(PinName pin); + virtual ~InterruptIn(); + + int read(); +#ifdef MBED_OPERATORS + operator int(); + +#endif + + /** Attach a function to call when a rising edge occurs on the input + * + * @param fptr A pointer to a void function, or 0 to set as none + */ + void rise(void (*fptr)(void)); + + /** Attach a member function to call when a rising edge occurs on the input + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + */ + template + void rise(T* tptr, void (T::*mptr)(void)) { + _rise.attach(tptr, mptr); + gpio_irq_set(&gpio_irq, IRQ_RISE, 1); + } + + /** Attach a function to call when a falling edge occurs on the input + * + * @param fptr A pointer to a void function, or 0 to set as none + */ + void fall(void (*fptr)(void)); + + /** Attach a member function to call when a falling edge occurs on the input + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + */ + template + void fall(T* tptr, void (T::*mptr)(void)) { + _fall.attach(tptr, mptr); + gpio_irq_set(&gpio_irq, IRQ_FALL, 1); + } + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone + */ + void mode(PinMode pull); + + /** Enable IRQ. This method depends on hw implementation, might enable one + * port interrupts. For further information, check gpio_irq_enable(). + */ + void enable_irq(); + + /** Disable IRQ. This method depends on hw implementation, might disable one + * port interrupts. For further information, check gpio_irq_disable(). + */ + void disable_irq(); + + static void _irq_handler(uint32_t id, gpio_irq_event event); + +protected: + gpio_t gpio; + gpio_irq_t gpio_irq; + + FunctionPointer _rise; + FunctionPointer _fall; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/InterruptManager.h b/api/InterruptManager.h new file mode 100644 index 0000000..4959a64 --- /dev/null +++ b/api/InterruptManager.h @@ -0,0 +1,143 @@ +#ifndef MBED_INTERRUPTMANAGER_H +#define MBED_INTERRUPTMANAGER_H + +#include "cmsis.h" +#include "CallChain.h" +#include + +namespace mbed { + +/** Use this singleton if you need to chain interrupt handlers. + * + * Example (for LPC1768): + * @code + * #include "InterruptManager.h" + * #include "mbed.h" + * + * Ticker flipper; + * DigitalOut led1(LED1); + * DigitalOut led2(LED2); + * + * void flip(void) { + * led1 = !led1; + * } + * + * void handler(void) { + * led2 = !led1; + * } + * + * int main() { + * led1 = led2 = 0; + * flipper.attach(&flip, 1.0); + * InterruptManager::get()->add_handler(handler, TIMER3_IRQn); + * } + * @endcode + */ +class InterruptManager { +public: + /** Return the only instance of this class + */ + static InterruptManager* get(); + + /** Destroy the current instance of the interrupt manager + */ + static void destroy(); + + /** Add a handler for an interrupt at the end of the handler list + * + * @param function the handler to add + * @param irq interrupt number + * + * @returns + * The function object created for 'function' + */ + pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) { + return add_common(function, irq); + } + + /** Add a handler for an interrupt at the beginning of the handler list + * + * @param function the handler to add + * @param irq interrupt number + * + * @returns + * The function object created for 'function' + */ + pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) { + return add_common(function, irq, true); + } + + /** Add a handler for an interrupt at the end of the handler list + * + * @param tptr pointer to the object that has the handler function + * @param mptr pointer to the actual handler function + * @param irq interrupt number + * + * @returns + * The function object created for 'tptr' and 'mptr' + */ + template + pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) { + return add_common(tptr, mptr, irq); + } + + /** Add a handler for an interrupt at the beginning of the handler list + * + * @param tptr pointer to the object that has the handler function + * @param mptr pointer to the actual handler function + * @param irq interrupt number + * + * @returns + * The function object created for 'tptr' and 'mptr' + */ + template + pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) { + return add_common(tptr, mptr, irq, true); + } + + /** Remove a handler from an interrupt + * + * @param handler the function object for the handler to remove + * @param irq the interrupt number + * + * @returns + * true if the handler was found and removed, false otherwise + */ + bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq); + +private: + InterruptManager(); + ~InterruptManager(); + + // We declare the copy contructor and the assignment operator, but we don't + // implement them. This way, if someone tries to copy/assign our instance, + // he will get an error at compile time. + InterruptManager(const InterruptManager&); + InterruptManager& operator =(const InterruptManager&); + + template + pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) { + int irq_pos = get_irq_index(irq); + bool change = must_replace_vector(irq); + + pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr); + if (change) + NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper); + return pf; + } + + pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false); + bool must_replace_vector(IRQn_Type irq); + int get_irq_index(IRQn_Type irq); + void irq_helper(); + void add_helper(void (*function)(void), IRQn_Type irq, bool front=false); + static void static_irq_helper(); + + CallChain* _chains[NVIC_NUM_VECTORS]; + static InterruptManager* _instance; +}; + +} // namespace mbed + +#endif + diff --git a/api/LocalFileSystem.h b/api/LocalFileSystem.h new file mode 100644 index 0000000..9eb61a4 --- /dev/null +++ b/api/LocalFileSystem.h @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_LOCALFILESYSTEM_H +#define MBED_LOCALFILESYSTEM_H + +#include "platform.h" + +#if DEVICE_LOCALFILESYSTEM + +#include "FileSystemLike.h" + +namespace mbed { + +FILEHANDLE local_file_open(const char* name, int flags); + +class LocalFileHandle : public FileHandle { + +public: + LocalFileHandle(FILEHANDLE fh); + + virtual int close(); + + virtual ssize_t write(const void *buffer, size_t length); + + virtual ssize_t read(void *buffer, size_t length); + + virtual int isatty(); + + virtual off_t lseek(off_t position, int whence); + + virtual int fsync(); + + virtual off_t flen(); + +protected: + FILEHANDLE _fh; + int pos; +}; + +/** A filesystem for accessing the local mbed Microcontroller USB disk drive + * + * This allows programs to read and write files on the same disk drive that is used to program the + * mbed Microcontroller. Once created, the standard C file access functions are used to open, + * read and write files. + * + * Example: + * @code + * #include "mbed.h" + * + * LocalFileSystem local("local"); // Create the local filesystem under the name "local" + * + * int main() { + * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing + * fprintf(fp, "Hello World!"); + * fclose(fp); + * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system + * + * DIR *d = opendir("/local"); // Opens the root directory of the local file system + * struct dirent *p; + * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system + * printf("%s\n", p->d_name); // to stdout. + * } + * closedir(d); + * } + * @endcode + * + * @note + * If the microcontroller program makes an access to the local drive, it will be marked as "removed" + * on the Host computer. This means it is no longer accessible from the Host Computer. + * + * The drive will only re-appear when the microcontroller program exists. Note that if the program does + * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again! + */ +class LocalFileSystem : public FileSystemLike { + +public: + LocalFileSystem(const char* n) : FileSystemLike(n) { + + } + + virtual FileHandle *open(const char* name, int flags); + virtual int remove(const char *filename); + virtual DirHandle *opendir(const char *name); +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/LowPowerTicker.h b/api/LowPowerTicker.h new file mode 100644 index 0000000..540788c --- /dev/null +++ b/api/LowPowerTicker.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_LOWPOWERTICKER_H +#define MBED_LOWPOWERTICKER_H + +#include "platform.h" +#include "Ticker.h" + +#if DEVICE_LOWPOWERTIMER + +#include "lp_ticker_api.h" + +namespace mbed { + +/** Low Power Ticker + */ +class LowPowerTicker : public Ticker { + +public: + LowPowerTicker() : Ticker(get_lp_ticker_data()) { + } + + virtual ~LowPowerTicker() { + } +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/LowPowerTimeout.h b/api/LowPowerTimeout.h new file mode 100644 index 0000000..c81e049 --- /dev/null +++ b/api/LowPowerTimeout.h @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_LOWPOWERTIMEOUT_H +#define MBED_LOWPOWERTIMEOUT_H + +#include "platform.h" + +#if DEVICE_LOWPOWERTIMER + +#include "lp_ticker_api.h" +#include "LowPowerTicker.h" + +namespace mbed { + +/** Low Power Timout + */ +class LowPowerTimeout : public LowPowerTicker { + +private: + virtual void handler(void) { + _function.call(); + } +}; + +} + +#endif + +#endif diff --git a/api/LowPowerTimer.h b/api/LowPowerTimer.h new file mode 100644 index 0000000..ad7782b --- /dev/null +++ b/api/LowPowerTimer.h @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_LOWPOWERTIMER_H +#define MBED_LOWPOWERTIMER_H + +#include "platform.h" +#include "Timer.h" + +#if DEVICE_LOWPOWERTIMER + +#include "lp_ticker_api.h" + +namespace mbed { + +/** Low power timer + */ +class LowPowerTimer : public Timer { + +public: + LowPowerTimer() : Timer(get_lp_ticker_data()) { + } + +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/PortIn.h b/api/PortIn.h new file mode 100644 index 0000000..4468632 --- /dev/null +++ b/api/PortIn.h @@ -0,0 +1,93 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTIN_H +#define MBED_PORTIN_H + +#include "platform.h" + +#if DEVICE_PORTIN + +#include "port_api.h" + +namespace mbed { + +/** A multiple pin digital input + * + * Example: + * @code + * // Switch on an LED if any of mbed pins 21-26 is high + * + * #include "mbed.h" + * + * PortIn p(Port2, 0x0000003F); // p21-p26 + * DigitalOut ind(LED4); + * + * int main() { + * while(1) { + * int pins = p.read(); + * if(pins) { + * ind = 1; + * } else { + * ind = 0; + * } + * } + * } + * @endcode + */ +class PortIn { +public: + + /** Create an PortIn, connected to the specified port + * + * @param port Port to connect to (Port0-Port5) + * @param mask A bitmask to identify which bits in the port should be included (0 - ignore) + */ + PortIn(PortName port, int mask = 0xFFFFFFFF) { + port_init(&_port, port, mask, PIN_INPUT); + } + + /** Read the value currently output on the port + * + * @returns + * An integer with each bit corresponding to associated port pin setting + */ + int read() { + return port_read(&_port); + } + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone, OpenDrain + */ + void mode(PinMode mode) { + port_mode(&_port, mode); + } + + /** A shorthand for read() + */ + operator int() { + return read(); + } + +private: + port_t _port; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/PortInOut.h b/api/PortInOut.h new file mode 100644 index 0000000..cca7551 --- /dev/null +++ b/api/PortInOut.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTINOUT_H +#define MBED_PORTINOUT_H + +#include "platform.h" + +#if DEVICE_PORTINOUT + +#include "port_api.h" + +namespace mbed { + +/** A multiple pin digital in/out used to set/read multiple bi-directional pins + */ +class PortInOut { +public: + + /** Create an PortInOut, connected to the specified port + * + * @param port Port to connect to (Port0-Port5) + * @param mask A bitmask to identify which bits in the port should be included (0 - ignore) + */ + PortInOut(PortName port, int mask = 0xFFFFFFFF) { + port_init(&_port, port, mask, PIN_INPUT); + } + + /** Write the value to the output port + * + * @param value An integer specifying a bit to write for every corresponding port pin + */ + void write(int value) { + port_write(&_port, value); + } + + /** Read the value currently output on the port + * + * @returns + * An integer with each bit corresponding to associated port pin setting + */ + int read() { + return port_read(&_port); + } + + /** Set as an output + */ + void output() { + port_dir(&_port, PIN_OUTPUT); + } + + /** Set as an input + */ + void input() { + port_dir(&_port, PIN_INPUT); + } + + /** Set the input pin mode + * + * @param mode PullUp, PullDown, PullNone, OpenDrain + */ + void mode(PinMode mode) { + port_mode(&_port, mode); + } + + /** A shorthand for write() + */ + PortInOut& operator= (int value) { + write(value); + return *this; + } + + PortInOut& operator= (PortInOut& rhs) { + write(rhs.read()); + return *this; + } + + /** A shorthand for read() + */ + operator int() { + return read(); + } + +private: + port_t _port; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/PortOut.h b/api/PortOut.h new file mode 100644 index 0000000..bab5fe0 --- /dev/null +++ b/api/PortOut.h @@ -0,0 +1,104 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTOUT_H +#define MBED_PORTOUT_H + +#include "platform.h" + +#if DEVICE_PORTOUT + +#include "port_api.h" + +namespace mbed { +/** A multiple pin digital out + * + * Example: + * @code + * // Toggle all four LEDs + * + * #include "mbed.h" + * + * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23 + * #define LED_MASK 0x00B40000 + * + * PortOut ledport(Port1, LED_MASK); + * + * int main() { + * while(1) { + * ledport = LED_MASK; + * wait(1); + * ledport = 0; + * wait(1); + * } + * } + * @endcode + */ +class PortOut { +public: + + /** Create an PortOut, connected to the specified port + * + * @param port Port to connect to (Port0-Port5) + * @param mask A bitmask to identify which bits in the port should be included (0 - ignore) + */ + PortOut(PortName port, int mask = 0xFFFFFFFF) { + port_init(&_port, port, mask, PIN_OUTPUT); + } + + /** Write the value to the output port + * + * @param value An integer specifying a bit to write for every corresponding PortOut pin + */ + void write(int value) { + port_write(&_port, value); + } + + /** Read the value currently output on the port + * + * @returns + * An integer with each bit corresponding to associated PortOut pin setting + */ + int read() { + return port_read(&_port); + } + + /** A shorthand for write() + */ + PortOut& operator= (int value) { + write(value); + return *this; + } + + PortOut& operator= (PortOut& rhs) { + write(rhs.read()); + return *this; + } + + /** A shorthand for read() + */ + operator int() { + return read(); + } + +private: + port_t _port; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/PwmOut.h b/api/PwmOut.h new file mode 100644 index 0000000..9e8c0bd --- /dev/null +++ b/api/PwmOut.h @@ -0,0 +1,158 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PWMOUT_H +#define MBED_PWMOUT_H + +#include "platform.h" + +#if DEVICE_PWMOUT +#include "pwmout_api.h" + +namespace mbed { + +/** A pulse-width modulation digital output + * + * Example + * @code + * // Fade a led on. + * #include "mbed.h" + * + * PwmOut led(LED1); + * + * int main() { + * while(1) { + * led = led + 0.01; + * wait(0.2); + * if(led == 1.0) { + * led = 0; + * } + * } + * } + * @endcode + * + * @note + * On the LPC1768 and LPC2368, the PWMs all share the same + * period - if you change the period for one, you change it for all. + * Although routines that change the period maintain the duty cycle + * for its PWM, all other PWMs will require their duty cycle to be + * refreshed. + */ +class PwmOut { + +public: + + /** Create a PwmOut connected to the specified pin + * + * @param pin PwmOut pin to connect to + */ + PwmOut(PinName pin) { + pwmout_init(&_pwm, pin); + } + + /** Set the ouput duty-cycle, specified as a percentage (float) + * + * @param value A floating-point value representing the output duty-cycle, + * specified as a percentage. The value should lie between + * 0.0f (representing on 0%) and 1.0f (representing on 100%). + * Values outside this range will be saturated to 0.0f or 1.0f. + */ + void write(float value) { + pwmout_write(&_pwm, value); + } + + /** Return the current output duty-cycle setting, measured as a percentage (float) + * + * @returns + * A floating-point value representing the current duty-cycle being output on the pin, + * measured as a percentage. The returned value will lie between + * 0.0f (representing on 0%) and 1.0f (representing on 100%). + * + * @note + * This value may not match exactly the value set by a previous . + */ + float read() { + return pwmout_read(&_pwm); + } + + /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same. + * + * @note + * The resolution is currently in microseconds; periods smaller than this + * will be set to zero. + */ + void period(float seconds) { + pwmout_period(&_pwm, seconds); + } + + /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same. + */ + void period_ms(int ms) { + pwmout_period_ms(&_pwm, ms); + } + + /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same. + */ + void period_us(int us) { + pwmout_period_us(&_pwm, us); + } + + /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same. + */ + void pulsewidth(float seconds) { + pwmout_pulsewidth(&_pwm, seconds); + } + + /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same. + */ + void pulsewidth_ms(int ms) { + pwmout_pulsewidth_ms(&_pwm, ms); + } + + /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same. + */ + void pulsewidth_us(int us) { + pwmout_pulsewidth_us(&_pwm, us); + } + +#ifdef MBED_OPERATORS + /** A operator shorthand for write() + */ + PwmOut& operator= (float value) { + write(value); + return *this; + } + + PwmOut& operator= (PwmOut& rhs) { + write(rhs.read()); + return *this; + } + + /** An operator shorthand for read() + */ + operator float() { + return read(); + } +#endif + +protected: + pwmout_t _pwm; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/RawSerial.h b/api/RawSerial.h new file mode 100644 index 0000000..a5182bb --- /dev/null +++ b/api/RawSerial.h @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RAW_SERIAL_H +#define MBED_RAW_SERIAL_H + +#include "platform.h" + +#if DEVICE_SERIAL + +#include "SerialBase.h" +#include "serial_api.h" + +namespace mbed { + +/** A serial port (UART) for communication with other serial devices + * This is a variation of the Serial class that doesn't use streams, + * thus making it safe to use in interrupt handlers with the RTOS. + * + * Can be used for Full Duplex communication, or Simplex by specifying + * one pin as NC (Not Connected) + * + * Example: + * @code + * // Send a char to the PC + * + * #include "mbed.h" + * + * RawSerial pc(USBTX, USBRX); + * + * int main() { + * pc.putc('A'); + * } + * @endcode + */ +class RawSerial: public SerialBase { + +public: + /** Create a RawSerial port, connected to the specified transmit and receive pins + * + * @param tx Transmit pin + * @param rx Receive pin + * + * @note + * Either tx or rx may be specified as NC if unused + */ + RawSerial(PinName tx, PinName rx); + + /** Write a char to the serial port + * + * @param c The char to write + * + * @returns The written char or -1 if an error occured + */ + int putc(int c); + + /** Read a char from the serial port + * + * @returns The char read from the serial port + */ + int getc(); + + /** Write a string to the serial port + * + * @param str The string to write + * + * @returns 0 if the write succeeds, EOF for error + */ + int puts(const char *str); + + int printf(const char *format, ...); +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/SPI.h b/api/SPI.h new file mode 100644 index 0000000..63eba25 --- /dev/null +++ b/api/SPI.h @@ -0,0 +1,245 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SPI_H +#define MBED_SPI_H + +#include "platform.h" + +#if DEVICE_SPI + +#include "spi_api.h" + +#if DEVICE_SPI_ASYNCH +#include "CThunk.h" +#include "dma_api.h" +#include "CircularBuffer.h" +#include "FunctionPointer.h" +#include "Transaction.h" +#endif + +namespace mbed { + +/** A SPI Master, used for communicating with SPI slave devices + * + * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz + * + * Most SPI devices will also require Chip Select and Reset signals. These + * can be controlled using pins + * + * Example: + * @code + * // Send a byte to a SPI slave, and record the response + * + * #include "mbed.h" + * + * // hardware ssel (where applicable) + * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel + * + * // software ssel + * SPI device(p5, p6, p7); // mosi, miso, sclk + * DigitalOut cs(p8); // ssel + * + * int main() { + * // hardware ssel (where applicable) + * //int response = device.write(0xFF); + * + * // software ssel + * cs = 0; + * int response = device.write(0xFF); + * cs = 1; + * } + * @endcode + */ +class SPI { + +public: + + /** Create a SPI master connected to the specified pins + * + * mosi or miso can be specfied as NC if not used + * + * @param mosi SPI Master Out, Slave In pin + * @param miso SPI Master In, Slave Out pin + * @param sclk SPI Clock pin + * @param ssel SPI chip select pin + */ + SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC); + + /** Configure the data transmission format + * + * @param bits Number of bits per SPI frame (4 - 16) + * @param mode Clock polarity and phase mode (0 - 3) + * + * @code + * mode | POL PHA + * -----+-------- + * 0 | 0 0 + * 1 | 0 1 + * 2 | 1 0 + * 3 | 1 1 + * @endcode + */ + void format(int bits, int mode = 0); + + /** Set the spi bus clock frequency + * + * @param hz SCLK frequency in hz (default = 1MHz) + */ + void frequency(int hz = 1000000); + + /** Write to the SPI Slave and return the response + * + * @param value Data to be sent to the SPI slave + * + * @returns + * Response from the SPI slave + */ + virtual int write(int value); + +#if DEVICE_SPI_ASYNCH + + /** Start non-blocking SPI transfer using 8bit buffers. + * + * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed, + * the default SPI value is sent + * @param tx_length The length of TX buffer in bytes + * @param rx_buffer The RX buffer which is used for received data. If NULL is passed, + * received data are ignored + * @param rx_length The length of RX buffer in bytes + * @param callback The event callback function + * @param event The logical OR of events to modify. Look at spi hal header file for SPI events. + * @return Zero if the transfer has started, or -1 if SPI peripheral is busy + */ + template + int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) { + if (spi_active(&_spi)) { + return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event); + } + start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event); + return 0; + } + + /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any. + */ + void abort_transfer(); + + /** Clear the transaction buffer + */ + void clear_transfer_buffer(); + + /** Clear the transaction buffer and abort on-going transfer. + */ + void abort_all_transfers(); + + /** Configure DMA usage suggestion for non-blocking transfers + * + * @param usage The usage DMA hint for peripheral + * @return Zero if the usage was set, -1 if a transaction is on-going + */ + int set_dma_usage(DMAUsage usage); + +protected: + /** SPI IRQ handler + * + */ + void irq_handler_asynch(void); + + /** Common transfer method + * + * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed, + * the default SPI value is sent + * @param tx_length The length of TX buffer in bytes + * @param rx_buffer The RX buffer which is used for received data. If NULL is passed, + * received data are ignored + * @param rx_length The length of RX buffer in bytes + * @param bit_width The buffers element width + * @param callback The event callback function + * @param event The logical OR of events to modify + * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full + */ + int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event); + + /** + * + * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed, + * the default SPI value is sent + * @param tx_length The length of TX buffer in bytes + * @param rx_buffer The RX buffer which is used for received data. If NULL is passed, + * received data are ignored + * @param rx_length The length of RX buffer in bytes + * @param bit_width The buffers element width + * @param callback The event callback function + * @param event The logical OR of events to modify + * @return Zero if a transfer was added to the queue, or -1 if the queue is full + */ + int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event); + + /** Configures a callback, spi peripheral and initiate a new transfer + * + * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed, + * the default SPI value is sent + * @param tx_length The length of TX buffer in bytes + * @param rx_buffer The RX buffer which is used for received data. If NULL is passed, + * received data are ignored + * @param rx_length The length of RX buffer in bytes + * @param bit_width The buffers element width + * @param callback The event callback function + * @param event The logical OR of events to modify + */ + void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event); + +#if TRANSACTION_QUEUE_SIZE_SPI + + /** Start a new transaction + * + * @param data Transaction data + */ + void start_transaction(transaction_t *data); + + /** Dequeue a transaction + * + */ + void dequeue_transaction(); + static CircularBuffer, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer; +#endif + +#endif + +public: + virtual ~SPI() { + } + +protected: + spi_t _spi; + +#if DEVICE_SPI_ASYNCH + CThunk _irq; + event_callback_t _callback; + DMAUsage _usage; +#endif + + void aquire(void); + static SPI *_owner; + int _bits; + int _mode; + int _hz; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/SPISlave.h b/api/SPISlave.h new file mode 100644 index 0000000..1875ff6 --- /dev/null +++ b/api/SPISlave.h @@ -0,0 +1,122 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SPISLAVE_H +#define MBED_SPISLAVE_H + +#include "platform.h" + +#if DEVICE_SPISLAVE + +#include "spi_api.h" + +namespace mbed { + +/** A SPI slave, used for communicating with a SPI Master device + * + * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz + * + * Example: + * @code + * // Reply to a SPI master as slave + * + * #include "mbed.h" + * + * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel + * + * int main() { + * device.reply(0x00); // Prime SPI with first reply + * while(1) { + * if(device.receive()) { + * int v = device.read(); // Read byte from master + * v = (v + 1) % 0x100; // Add one to it, modulo 256 + * device.reply(v); // Make this the next reply + * } + * } + * } + * @endcode + */ +class SPISlave { + +public: + + /** Create a SPI slave connected to the specified pins + * + * mosi or miso can be specfied as NC if not used + * + * @param mosi SPI Master Out, Slave In pin + * @param miso SPI Master In, Slave Out pin + * @param sclk SPI Clock pin + * @param ssel SPI chip select pin + */ + SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel); + + /** Configure the data transmission format + * + * @param bits Number of bits per SPI frame (4 - 16) + * @param mode Clock polarity and phase mode (0 - 3) + * + * @code + * mode | POL PHA + * -----+-------- + * 0 | 0 0 + * 1 | 0 1 + * 2 | 1 0 + * 3 | 1 1 + * @endcode + */ + void format(int bits, int mode = 0); + + /** Set the spi bus clock frequency + * + * @param hz SCLK frequency in hz (default = 1MHz) + */ + void frequency(int hz = 1000000); + + /** Polls the SPI to see if data has been received + * + * @returns + * 0 if no data, + * 1 otherwise + */ + int receive(void); + + /** Retrieve data from receive buffer as slave + * + * @returns + * the data in the receive buffer + */ + int read(void); + + /** Fill the transmission buffer with the value to be written out + * as slave on the next received message from the master. + * + * @param value the data to be transmitted next + */ + void reply(int value); + +protected: + spi_t _spi; + + int _bits; + int _mode; + int _hz; +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/Serial.h b/api/Serial.h new file mode 100644 index 0000000..aa06540 --- /dev/null +++ b/api/Serial.h @@ -0,0 +1,74 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SERIAL_H +#define MBED_SERIAL_H + +#include "platform.h" + +#if DEVICE_SERIAL + +#include "Stream.h" +#include "SerialBase.h" +#include "serial_api.h" + +namespace mbed { + +/** A serial port (UART) for communication with other serial devices + * + * Can be used for Full Duplex communication, or Simplex by specifying + * one pin as NC (Not Connected) + * + * Example: + * @code + * // Print "Hello World" to the PC + * + * #include "mbed.h" + * + * Serial pc(USBTX, USBRX); + * + * int main() { + * pc.printf("Hello World\n"); + * } + * @endcode + */ +class Serial : public SerialBase, public Stream { + +public: +#if DEVICE_SERIAL_ASYNCH + using SerialBase::read; + using SerialBase::write; +#endif + + /** Create a Serial port, connected to the specified transmit and receive pins + * + * @param tx Transmit pin + * @param rx Receive pin + * + * @note + * Either tx or rx may be specified as NC if unused + */ + Serial(PinName tx, PinName rx, const char *name=NULL); + +protected: + virtual int _getc(); + virtual int _putc(int c); +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/SerialBase.h b/api/SerialBase.h new file mode 100644 index 0000000..51aeb33 --- /dev/null +++ b/api/SerialBase.h @@ -0,0 +1,223 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SERIALBASE_H +#define MBED_SERIALBASE_H + +#include "platform.h" + +#if DEVICE_SERIAL + +#include "Stream.h" +#include "FunctionPointer.h" +#include "serial_api.h" + +#if DEVICE_SERIAL_ASYNCH +#include "CThunk.h" +#include "dma_api.h" +#endif + +namespace mbed { + +/** A base class for serial port implementations + * Can't be instantiated directly (use Serial or RawSerial) + */ +class SerialBase { + +public: + /** Set the baud rate of the serial port + * + * @param baudrate The baudrate of the serial port (default = 9600). + */ + void baud(int baudrate); + + enum Parity { + None = 0, + Odd, + Even, + Forced1, + Forced0 + }; + + enum IrqType { + RxIrq = 0, + TxIrq + }; + + enum Flow { + Disabled = 0, + RTS, + CTS, + RTSCTS + }; + + /** Set the transmission format used by the serial port + * + * @param bits The number of bits in a word (5-8; default = 8) + * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None) + * @param stop The number of stop bits (1 or 2; default = 1) + */ + void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1); + + /** Determine if there is a character available to read + * + * @returns + * 1 if there is a character available to read, + * 0 otherwise + */ + int readable(); + + /** Determine if there is space available to write a character + * + * @returns + * 1 if there is space to write a character, + * 0 otherwise + */ + int writeable(); + + /** Attach a function to call whenever a serial interrupt is generated + * + * @param fptr A pointer to a void function, or 0 to set as none + * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) + */ + void attach(void (*fptr)(void), IrqType type=RxIrq); + + /** Attach a member function to call whenever a serial interrupt is generated + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty) + */ + template + void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) { + if((mptr != NULL) && (tptr != NULL)) { + _irq[type].attach(tptr, mptr); + serial_irq_set(&_serial, (SerialIrq)type, 1); + } else { + serial_irq_set(&_serial, (SerialIrq)type, 0); + } + } + + /** Generate a break condition on the serial line + */ + void send_break(); + +#if DEVICE_SERIAL_FC + /** Set the flow control type on the serial port + * + * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) + * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) + * @param flow2 the second flow control pin (CTS for RTSCTS) + */ + void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC); +#endif + + static void _irq_handler(uint32_t id, SerialIrq irq_type); + +#if DEVICE_SERIAL_ASYNCH + + /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback + * + * @param buffer The buffer where received data will be stored + * @param length The buffer length in bytes + * @param callback The event callback function + * @param event The logical OR of TX events + */ + int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE); + + /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback + * + * @param buffer The buffer where received data will be stored + * @param length The buffer length in bytes + * @param callback The event callback function + * @param event The logical OR of TX events + */ + int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE); + + /** Abort the on-going write transfer + */ + void abort_write(); + + /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback. + * + * @param buffer The buffer where received data will be stored + * @param length The buffer length in bytes + * @param callback The event callback function + * @param event The logical OR of RX events + * @param char_match The matching character + */ + int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH); + + /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback. + * + * @param buffer The buffer where received data will be stored + * @param length The buffer length in bytes + * @param callback The event callback function + * @param event The logical OR of RX events + * @param char_match The matching character + */ + int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH); + + /** Abort the on-going read transfer + */ + void abort_read(); + + /** Configure DMA usage suggestion for non-blocking TX transfers + * + * @param usage The usage DMA hint for peripheral + * @return Zero if the usage was set, -1 if a transaction is on-going + */ + int set_dma_usage_tx(DMAUsage usage); + + /** Configure DMA usage suggestion for non-blocking RX transfers + * + * @param usage The usage DMA hint for peripheral + * @return Zero if the usage was set, -1 if a transaction is on-going + */ + int set_dma_usage_rx(DMAUsage usage); + +protected: + void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match); + void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event); + void interrupt_handler_asynch(void); +#endif + +protected: + SerialBase(PinName tx, PinName rx); + virtual ~SerialBase() { + } + + int _base_getc(); + int _base_putc(int c); + +#if DEVICE_SERIAL_ASYNCH + CThunk _thunk_irq; + event_callback_t _tx_callback; + event_callback_t _rx_callback; + DMAUsage _tx_usage; + DMAUsage _rx_usage; +#endif + + serial_t _serial; + FunctionPointer _irq[2]; + int _baud; + +}; + +} // namespace mbed + +#endif + +#endif diff --git a/api/Stream.h b/api/Stream.h new file mode 100644 index 0000000..a57053e --- /dev/null +++ b/api/Stream.h @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_STREAM_H +#define MBED_STREAM_H + +#include "platform.h" +#include "FileLike.h" + +namespace mbed { + +extern void mbed_set_unbuffered_stream(FILE *_file); +extern int mbed_getc(FILE *_file); +extern char* mbed_gets(char *s, int size, FILE *_file); + +class Stream : public FileLike { + +public: + Stream(const char *name=NULL); + virtual ~Stream(); + + int putc(int c); + int puts(const char *s); + int getc(); + char *gets(char *s, int size); + int printf(const char* format, ...); + int scanf(const char* format, ...); + + operator std::FILE*() {return _file;} + +protected: + virtual int close(); + virtual ssize_t write(const void* buffer, size_t length); + virtual ssize_t read(void* buffer, size_t length); + virtual off_t lseek(off_t offset, int whence); + virtual int isatty(); + virtual int fsync(); + virtual off_t flen(); + + virtual int _putc(int c) = 0; + virtual int _getc() = 0; + + std::FILE *_file; + + /* disallow copy constructor and assignment operators */ +private: + Stream(const Stream&); + Stream & operator = (const Stream&); +}; + +} // namespace mbed + +#endif diff --git a/api/Ticker.h b/api/Ticker.h new file mode 100644 index 0000000..fda205d --- /dev/null +++ b/api/Ticker.h @@ -0,0 +1,127 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TICKER_H +#define MBED_TICKER_H + +#include "TimerEvent.h" +#include "FunctionPointer.h" + +namespace mbed { + +/** A Ticker is used to call a function at a recurring interval + * + * You can use as many seperate Ticker objects as you require. + * + * Example: + * @code + * // Toggle the blinking led after 5 seconds + * + * #include "mbed.h" + * + * Ticker timer; + * DigitalOut led1(LED1); + * DigitalOut led2(LED2); + * + * int flip = 0; + * + * void attime() { + * flip = !flip; + * } + * + * int main() { + * timer.attach(&attime, 5); + * while(1) { + * if(flip == 0) { + * led1 = !led1; + * } else { + * led2 = !led2; + * } + * wait(0.2); + * } + * } + * @endcode + */ +class Ticker : public TimerEvent { + +public: + Ticker() : TimerEvent() { + } + + Ticker(const ticker_data_t *data) : TimerEvent(data) { + } + + /** Attach a function to be called by the Ticker, specifiying the interval in seconds + * + * @param fptr pointer to the function to be called + * @param t the time between calls in seconds + */ + void attach(void (*fptr)(void), float t) { + attach_us(fptr, t * 1000000.0f); + } + + /** Attach a member function to be called by the Ticker, specifiying the interval in seconds + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + * @param t the time between calls in seconds + */ + template + void attach(T* tptr, void (T::*mptr)(void), float t) { + attach_us(tptr, mptr, t * 1000000.0f); + } + + /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds + * + * @param fptr pointer to the function to be called + * @param t the time between calls in micro-seconds + */ + void attach_us(void (*fptr)(void), timestamp_t t) { + _function.attach(fptr); + setup(t); + } + + /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds + * + * @param tptr pointer to the object to call the member function on + * @param mptr pointer to the member function to be called + * @param t the time between calls in micro-seconds + */ + template + void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) { + _function.attach(tptr, mptr); + setup(t); + } + + virtual ~Ticker() { + detach(); + } + + /** Detach the function + */ + void detach(); + +protected: + void setup(timestamp_t t); + virtual void handler(); + +protected: + timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */ + FunctionPointer _function; /**< Callback. */ +}; + +} // namespace mbed + +#endif diff --git a/api/Timeout.h b/api/Timeout.h new file mode 100644 index 0000000..e145d9a --- /dev/null +++ b/api/Timeout.h @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TIMEOUT_H +#define MBED_TIMEOUT_H + +#include "Ticker.h" + +namespace mbed { + +/** A Timeout is used to call a function at a point in the future + * + * You can use as many seperate Timeout objects as you require. + * + * Example: + * @code + * // Blink until timeout. + * + * #include "mbed.h" + * + * Timeout timeout; + * DigitalOut led(LED1); + * + * int on = 1; + * + * void attimeout() { + * on = 0; + * } + * + * int main() { + * timeout.attach(&attimeout, 5); + * while(on) { + * led = !led; + * wait(0.2); + * } + * } + * @endcode + */ +class Timeout : public Ticker { + +protected: + virtual void handler(); +}; + +} // namespace mbed + +#endif diff --git a/api/Timer.h b/api/Timer.h new file mode 100644 index 0000000..78faf60 --- /dev/null +++ b/api/Timer.h @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TIMER_H +#define MBED_TIMER_H + +#include "platform.h" +#include "ticker_api.h" + +namespace mbed { + +/** A general purpose timer + * + * Example: + * @code + * // Count the time to toggle a LED + * + * #include "mbed.h" + * + * Timer timer; + * DigitalOut led(LED1); + * int begin, end; + * + * int main() { + * timer.start(); + * begin = timer.read_us(); + * led = !led; + * end = timer.read_us(); + * printf("Toggle the led takes %d us", end - begin); + * } + * @endcode + */ +class Timer { + +public: + Timer(); + Timer(const ticker_data_t *data); + + /** Start the timer + */ + void start(); + + /** Stop the timer + */ + void stop(); + + /** Reset the timer to 0. + * + * If it was already counting, it will continue + */ + void reset(); + + /** Get the time passed in seconds + */ + float read(); + + /** Get the time passed in mili-seconds + */ + int read_ms(); + + /** Get the time passed in micro-seconds + */ + int read_us(); + +#ifdef MBED_OPERATORS + operator float(); +#endif + +protected: + int slicetime(); + int _running; // whether the timer is running + unsigned int _start; // the start time of the latest slice + int _time; // any accumulated time from previous slices + const ticker_data_t *_ticker_data; +}; + +} // namespace mbed + +#endif diff --git a/api/TimerEvent.h b/api/TimerEvent.h new file mode 100644 index 0000000..cee6fb2 --- /dev/null +++ b/api/TimerEvent.h @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TIMEREVENT_H +#define MBED_TIMEREVENT_H + +#include "ticker_api.h" +#include "us_ticker_api.h" + +namespace mbed { + +/** Base abstraction for timer interrupts +*/ +class TimerEvent { +public: + TimerEvent(); + TimerEvent(const ticker_data_t *data); + + /** The handler registered with the underlying timer interrupt + */ + static void irq(uint32_t id); + + /** Destruction removes it... + */ + virtual ~TimerEvent(); + +protected: + // The handler called to service the timer event of the derived class + virtual void handler() = 0; + + // insert in to linked list + void insert(timestamp_t timestamp); + + // remove from linked list, if in it + void remove(); + + ticker_event_t event; + + const ticker_data_t *_ticker_data; +}; + +} // namespace mbed + +#endif diff --git a/api/Transaction.h b/api/Transaction.h new file mode 100644 index 0000000..92852e2 --- /dev/null +++ b/api/Transaction.h @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TRANSACTION_H +#define MBED_TRANSACTION_H + +#include "platform.h" +#include "FunctionPointer.h" + +namespace mbed { + +/** Transaction structure + */ +typedef struct { + void *tx_buffer; /**< Tx buffer */ + size_t tx_length; /**< Length of Tx buffer*/ + void *rx_buffer; /**< Rx buffer */ + size_t rx_length; /**< Length of Rx buffer */ + uint32_t event; /**< Event for a transaction */ + event_callback_t callback; /**< User's callback */ + uint8_t width; /**< Buffer's word width (8, 16, 32, 64) */ +} transaction_t; + +/** Transaction class defines a transaction. + */ +template +class Transaction { +public: + Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) { + } + + Transaction() : _obj(), _data() { + } + + ~Transaction() { + } + + /** Get object's instance for the transaction + * + * @return The object which was stored + */ + Class* get_object() { + return _obj; + } + + /** Get the transaction + * + * @return The transaction which was stored + */ + transaction_t* get_transaction() { + return &_data; + } + +private: + Class* _obj; + transaction_t _data; +}; + +} + +#endif diff --git a/api/can_helper.h b/api/can_helper.h new file mode 100644 index 0000000..e427250 --- /dev/null +++ b/api/can_helper.h @@ -0,0 +1,53 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CAN_HELPER_H +#define MBED_CAN_HELPER_H + +#if DEVICE_CAN + +#ifdef __cplusplus +extern "C" { +#endif + +enum CANFormat { + CANStandard = 0, + CANExtended = 1, + CANAny = 2 +}; +typedef enum CANFormat CANFormat; + +enum CANType { + CANData = 0, + CANRemote = 1 +}; +typedef enum CANType CANType; + +struct CAN_Message { + unsigned int id; // 29 bit identifier + unsigned char data[8]; // Data field + unsigned char len; // Length of data field in bytes + CANFormat format; // 0 - STANDARD, 1- EXTENDED IDENTIFIER + CANType type; // 0 - DATA FRAME, 1 - REMOTE FRAME +}; +typedef struct CAN_Message CAN_Message; + +#ifdef __cplusplus +}; +#endif + +#endif + +#endif // MBED_CAN_HELPER_H diff --git a/api/mbed.h b/api/mbed.h new file mode 100644 index 0000000..68bdf52 --- /dev/null +++ b/api/mbed.h @@ -0,0 +1,69 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_H +#define MBED_H + +#define MBED_LIBRARY_VERSION 103 + +#include "platform.h" + +// Useful C libraries +#include +#include + +// mbed Debug libraries +#include "mbed_error.h" +#include "mbed_interface.h" + +// mbed Peripheral components +#include "DigitalIn.h" +#include "DigitalOut.h" +#include "DigitalInOut.h" +#include "BusIn.h" +#include "BusOut.h" +#include "BusInOut.h" +#include "PortIn.h" +#include "PortInOut.h" +#include "PortOut.h" +#include "AnalogIn.h" +#include "AnalogOut.h" +#include "PwmOut.h" +#include "Serial.h" +#include "SPI.h" +#include "SPISlave.h" +#include "I2C.h" +#include "I2CSlave.h" +#include "Ethernet.h" +#include "CAN.h" +#include "RawSerial.h" + +// mbed Internal components +#include "Timer.h" +#include "Ticker.h" +#include "Timeout.h" +#include "LowPowerTimeout.h" +#include "LowPowerTicker.h" +#include "LowPowerTimer.h" +#include "LocalFileSystem.h" +#include "InterruptIn.h" +#include "wait_api.h" +#include "sleep_api.h" +#include "rtc_time.h" + +using namespace mbed; +using namespace std; + +#endif diff --git a/api/mbed_assert.h b/api/mbed_assert.h new file mode 100644 index 0000000..7aed539 --- /dev/null +++ b/api/mbed_assert.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ASSERT_H +#define MBED_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes. + * This function is active only if NDEBUG is not defined prior to including this + * assert header file. + * In case of MBED_ASSERT failing condition, error() is called with the assertation message. + * @param expr Expresion to be checked. + * @param file File where assertation failed. + * @param line Failing assertation line number. + */ +void mbed_assert_internal(const char *expr, const char *file, int line); + +#ifdef __cplusplus +} +#endif + +#ifdef NDEBUG +#define MBED_ASSERT(expr) ((void)0) + +#else +#define MBED_ASSERT(expr) \ +do { \ + if (!(expr)) { \ + mbed_assert_internal(#expr, __FILE__, __LINE__); \ + } \ +} while (0) +#endif + +#endif diff --git a/api/mbed_debug.h b/api/mbed_debug.h new file mode 100644 index 0000000..2c8a346 --- /dev/null +++ b/api/mbed_debug.h @@ -0,0 +1,66 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEBUG_H +#define MBED_DEBUG_H +#include "device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if DEVICE_STDIO_MESSAGES +#include +#include + +/** Output a debug message + * + * @param format printf-style format string, followed by variables + */ +static inline void debug(const char *format, ...) { + va_list args; + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); +} + +/** Conditionally output a debug message + * + * NOTE: If the condition is constant false (!= 1) and the compiler optimization + * level is greater than 0, then the whole function will be compiled away. + * + * @param condition output only if condition is true (== 1) + * @param format printf-style format string, followed by variables + */ +static inline void debug_if(int condition, const char *format, ...) { + if (condition == 1) { + va_list args; + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); + } +} + +#else +static inline void debug(const char *format, ...) {} +static inline void debug_if(int condition, const char *format, ...) {} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/api/mbed_error.h b/api/mbed_error.h new file mode 100644 index 0000000..3a40358 --- /dev/null +++ b/api/mbed_error.h @@ -0,0 +1,66 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ERROR_H +#define MBED_ERROR_H + +/** To generate a fatal compile-time error, you can use the pre-processor #error directive. + * + * @code + * #error "That shouldn't have happened!" + * @endcode + * + * If the compiler evaluates this line, it will report the error and stop the compile. + * + * For example, you could use this to check some user-defined compile-time variables: + * + * @code + * #define NUM_PORTS 7 + * #if (NUM_PORTS > 4) + * #error "NUM_PORTS must be less than 4" + * #endif + * @endcode + * + * Reporting Run-Time Errors: + * To generate a fatal run-time error, you can use the mbed error() function. + * + * @code + * error("That shouldn't have happened!"); + * @endcode + * + * If the mbed running the program executes this function, it will print the + * message via the USB serial port, and then die with the blue lights of death! + * + * The message can use printf-style formatting, so you can report variables in the + * message too. For example, you could use this to check a run-time condition: + * + * @code + * if(x >= 5) { + * error("expected x to be less than 5, but got %d", x); + * } + * #endcode + */ + +#ifdef __cplusplus +extern "C" { +#endif + +void error(const char* format, ...); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/api/mbed_interface.h b/api/mbed_interface.h new file mode 100644 index 0000000..a93a4d3 --- /dev/null +++ b/api/mbed_interface.h @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_INTERFACE_H +#define MBED_INTERFACE_H + +#include "device.h" + +/* Mbed interface mac address + * if MBED_MAC_ADD_x are zero, interface uid sets mac address, + * otherwise MAC_ADD_x are used. + */ +#define MBED_MAC_ADDR_INTERFACE 0x00 +#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE +#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE +#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE +#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE +#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE +#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE +#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5) + +#ifdef __cplusplus +extern "C" { +#endif + +#if DEVICE_SEMIHOST + +/** Functions to control the mbed interface + * + * mbed Microcontrollers have a built-in interface to provide functionality such as + * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file + * system. These functions provide means to control the interface suing semihost + * calls it supports. + */ + +/** Determine whether the mbed interface is connected, based on whether debug is enabled + * + * @returns + * 1 if interface is connected, + * 0 otherwise + */ +int mbed_interface_connected(void); + +/** Instruct the mbed interface to reset, as if the reset button had been pressed + * + * @returns + * 1 if successful, + * 0 otherwise (e.g. interface not present) + */ +int mbed_interface_reset(void); + +/** This will disconnect the debug aspect of the interface, so semihosting will be disabled. + * The interface will still support the USB serial aspect + * + * @returns + * 0 if successful, + * -1 otherwise (e.g. interface not present) + */ +int mbed_interface_disconnect(void); + +/** This will disconnect the debug aspect of the interface, and if the USB cable is not + * connected, also power down the interface. If the USB cable is connected, the interface + * will remain powered up and visible to the host + * + * @returns + * 0 if successful, + * -1 otherwise (e.g. interface not present) + */ +int mbed_interface_powerdown(void); + +/** This returns a string containing the 32-character UID of the mbed interface + * This is a weak function that can be overwritten if required + * + * @param uid A 33-byte array to write the null terminated 32-byte string + * + * @returns + * 0 if successful, + * -1 otherwise (e.g. interface not present) + */ +int mbed_interface_uid(char *uid); + +#endif + +/** This returns a unique 6-byte MAC address, based on the interface UID + * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00) + * + * This is a weak function that can be overwritten if you want to provide your own mechanism to + * provide a MAC address. + * + * @param mac A 6-byte array to write the MAC address + */ +void mbed_mac_address(char *mac); + +/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence + */ +void mbed_die(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/api/platform.h b/api/platform.h new file mode 100644 index 0000000..85e44e5 --- /dev/null +++ b/api/platform.h @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PLATFORM_H +#define MBED_PLATFORM_H + +#define MBED_OPERATORS 1 + +#include "device.h" +#include "PinNames.h" +#include "PeripheralNames.h" + +#include +#include +#include +#include + +#endif diff --git a/api/rtc_time.h b/api/rtc_time.h new file mode 100644 index 0000000..5658973 --- /dev/null +++ b/api/rtc_time.h @@ -0,0 +1,85 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Implementation of the C time.h functions + * + * Provides mechanisms to set and read the current time, based + * on the microcontroller Real-Time Clock (RTC), plus some + * standard C manipulation and formating functions. + * + * Example: + * @code + * #include "mbed.h" + * + * int main() { + * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37 + * + * while(1) { + * time_t seconds = time(NULL); + * + * printf("Time as seconds since January 1, 1970 = %d\n", seconds); + * + * printf("Time as a basic string = %s", ctime(&seconds)); + * + * char buffer[32]; + * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds)); + * printf("Time as a custom formatted string = %s", buffer); + * + * wait(1); + * } + * } + * @endcode + */ + +/** Set the current time + * + * Initialises and sets the time of the microcontroller Real-Time Clock (RTC) + * to the time represented by the number of seconds since January 1, 1970 + * (the UNIX timestamp). + * + * @param t Number of seconds since January 1, 1970 (the UNIX timestamp) + * + * Example: + * @code + * #include "mbed.h" + * + * int main() { + * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37 + * } + * @endcode + */ +void set_time(time_t t); + +/** Attach an external RTC to be used for the C time functions + * + * Do not call this function from an interrupt while an RTC read/write operation may be occurring + * + * @param read_rtc pointer to function which returns current UNIX timestamp + * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL + * @param init_rtc pointer to funtion which initializes RTC, can be NULL + * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL + */ +void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)); + +#ifdef __cplusplus +} +#endif diff --git a/api/semihost_api.h b/api/semihost_api.h new file mode 100644 index 0000000..279f671 --- /dev/null +++ b/api/semihost_api.h @@ -0,0 +1,93 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SEMIHOST_H +#define MBED_SEMIHOST_H + +#include "device.h" +#include "toolchain.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if DEVICE_SEMIHOST + +#ifndef __CC_ARM + +#if defined(__ICCARM__) +inline int __semihost(int reason, const void *arg) { + return __semihosting(reason, (void*)arg); +} +#else + +#ifdef __thumb__ +# define AngelSWI 0xAB +# define AngelSWIInsn "bkpt" +# define AngelSWIAsm bkpt +#else +# define AngelSWI 0x123456 +# define AngelSWIInsn "swi" +# define AngelSWIAsm swi +#endif + +static inline int __semihost(int reason, const void *arg) { + int value; + + asm volatile ( + "mov r0, %1" "\n\t" + "mov r1, %2" "\n\t" + AngelSWIInsn " %a3" "\n\t" + "mov %0, r0" + : "=r" (value) /* output operands */ + : "r" (reason), "r" (arg), "i" (AngelSWI) /* input operands */ + : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */ + ); + + return value; +} +#endif +#endif + +#if DEVICE_LOCALFILESYSTEM +FILEHANDLE semihost_open(const char* name, int openmode); +int semihost_close (FILEHANDLE fh); +int semihost_read (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode); +int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode); +int semihost_ensure(FILEHANDLE fh); +long semihost_flen (FILEHANDLE fh); +int semihost_seek (FILEHANDLE fh, long position); +int semihost_istty (FILEHANDLE fh); + +int semihost_remove(const char *name); +int semihost_rename(const char *old_name, const char *new_name); +#endif + +int semihost_uid(char *uid); +int semihost_reset(void); +int semihost_vbus(void); +int semihost_powerdown(void); +int semihost_exit(void); + +int semihost_connected(void); +int semihost_disabledebug(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/api/toolchain.h b/api/toolchain.h new file mode 100644 index 0000000..b140643 --- /dev/null +++ b/api/toolchain.h @@ -0,0 +1,35 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TOOLCHAIN_H +#define MBED_TOOLCHAIN_H + +#if defined(TOOLCHAIN_ARM) +#include +#endif + +#ifndef FILEHANDLE +typedef int FILEHANDLE; +#endif + +#if defined (__ICCARM__) +# define WEAK __weak +# define PACKED __packed +#else +# define WEAK __attribute__((weak)) +# define PACKED __attribute__((packed)) +#endif + +#endif diff --git a/api/wait_api.h b/api/wait_api.h new file mode 100644 index 0000000..03c2714 --- /dev/null +++ b/api/wait_api.h @@ -0,0 +1,66 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_WAIT_API_H +#define MBED_WAIT_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** Generic wait functions. + * + * These provide simple NOP type wait capabilities. + * + * Example: + * @code + * #include "mbed.h" + * + * DigitalOut heartbeat(LED1); + * + * int main() { + * while (1) { + * heartbeat = 1; + * wait(0.5); + * heartbeat = 0; + * wait(0.5); + * } + * } + */ + +/** Waits for a number of seconds, with microsecond resolution (within + * the accuracy of single precision floating point). + * + * @param s number of seconds to wait + */ +void wait(float s); + +/** Waits a number of milliseconds. + * + * @param ms the whole number of milliseconds to wait + */ +void wait_ms(int ms); + +/** Waits a number of microseconds. + * + * @param us the whole number of microseconds to wait + */ +void wait_us(int us); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/common/BusIn.cpp b/common/BusIn.cpp new file mode 100644 index 0000000..ea67cbc --- /dev/null +++ b/common/BusIn.cpp @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "BusIn.h" +#include "mbed_assert.h" + +namespace mbed { + +BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { + PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + + _nc_mask = 0; + for (int i=0; i<16; i++) { + _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } + } +} + +BusIn::BusIn(PinName pins[16]) { + _nc_mask = 0; + for (int i=0; i<16; i++) { + _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } + } +} + +BusIn::~BusIn() { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + delete _pin[i]; + } + } +} + +int BusIn::read() { + int v = 0; + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + v |= _pin[i]->read() << i; + } + } + return v; +} + +void BusIn::mode(PinMode pull) { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + _pin[i]->mode(pull); + } + } +} + +#ifdef MBED_OPERATORS +BusIn::operator int() { + return read(); +} + +DigitalIn& BusIn::operator[] (int index) { + MBED_ASSERT(index >= 0 && index <= 16); + MBED_ASSERT(_pin[index]); + return *_pin[index]; +} + +#endif + +} // namespace mbed diff --git a/common/BusInOut.cpp b/common/BusInOut.cpp new file mode 100644 index 0000000..5575f90 --- /dev/null +++ b/common/BusInOut.cpp @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "BusInOut.h" +#include "mbed_assert.h" + +namespace mbed { + +BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { + PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + + _nc_mask = 0; + for (int i=0; i<16; i++) { + _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } + } +} + +BusInOut::BusInOut(PinName pins[16]) { + _nc_mask = 0; + for (int i=0; i<16; i++) { + _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } + } +} + +BusInOut::~BusInOut() { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + delete _pin[i]; + } + } +} + +void BusInOut::write(int value) { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + _pin[i]->write((value >> i) & 1); + } + } +} + +int BusInOut::read() { + int v = 0; + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + v |= _pin[i]->read() << i; + } + } + return v; +} + +void BusInOut::output() { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + _pin[i]->output(); + } + } +} + +void BusInOut::input() { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + _pin[i]->input(); + } + } +} + +void BusInOut::mode(PinMode pull) { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + _pin[i]->mode(pull); + } + } +} + +#ifdef MBED_OPERATORS +BusInOut& BusInOut::operator= (int v) { + write(v); + return *this; +} + +BusInOut& BusInOut::operator= (BusInOut& rhs) { + write(rhs.read()); + return *this; +} + +DigitalInOut& BusInOut::operator[] (int index) { + MBED_ASSERT(index >= 0 && index <= 16); + MBED_ASSERT(_pin[index]); + return *_pin[index]; +} + +BusInOut::operator int() { + return read(); +} +#endif + +} // namespace mbed diff --git a/common/BusOut.cpp b/common/BusOut.cpp new file mode 100644 index 0000000..4277c57 --- /dev/null +++ b/common/BusOut.cpp @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "BusOut.h" +#include "mbed_assert.h" + +namespace mbed { + +BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) { + PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}; + + _nc_mask = 0; + for (int i=0; i<16; i++) { + _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } + } +} + +BusOut::BusOut(PinName pins[16]) { + _nc_mask = 0; + for (int i=0; i<16; i++) { + _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0; + if (pins[i] != NC) { + _nc_mask |= (1 << i); + } + } +} + +BusOut::~BusOut() { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + delete _pin[i]; + } + } +} + +void BusOut::write(int value) { + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + _pin[i]->write((value >> i) & 1); + } + } +} + +int BusOut::read() { + int v = 0; + for (int i=0; i<16; i++) { + if (_pin[i] != 0) { + v |= _pin[i]->read() << i; + } + } + return v; +} + +#ifdef MBED_OPERATORS +BusOut& BusOut::operator= (int v) { + write(v); + return *this; +} + +BusOut& BusOut::operator= (BusOut& rhs) { + write(rhs.read()); + return *this; +} + +DigitalOut& BusOut::operator[] (int index) { + MBED_ASSERT(index >= 0 && index <= 16); + MBED_ASSERT(_pin[index]); + return *_pin[index]; +} + +BusOut::operator int() { + return read(); +} +#endif + +} // namespace mbed diff --git a/common/CAN.cpp b/common/CAN.cpp new file mode 100644 index 0000000..407e00b --- /dev/null +++ b/common/CAN.cpp @@ -0,0 +1,86 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "CAN.h" + +#if DEVICE_CAN + +#include "cmsis.h" + +namespace mbed { + +CAN::CAN(PinName rd, PinName td) : _can(), _irq() { + can_init(&_can, rd, td); + can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this); +} + +CAN::~CAN() { + can_irq_free(&_can); + can_free(&_can); +} + +int CAN::frequency(int f) { + return can_frequency(&_can, f); +} + +int CAN::write(CANMessage msg) { + return can_write(&_can, msg, 0); +} + +int CAN::read(CANMessage &msg, int handle) { + return can_read(&_can, &msg, handle); +} + +void CAN::reset() { + can_reset(&_can); +} + +unsigned char CAN::rderror() { + return can_rderror(&_can); +} + +unsigned char CAN::tderror() { + return can_tderror(&_can); +} + +void CAN::monitor(bool silent) { + can_monitor(&_can, (silent) ? 1 : 0); +} + +int CAN::mode(Mode mode) { + return can_mode(&_can, (CanMode)mode); +} + +int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) { + return can_filter(&_can, id, mask, format, handle); +} + +void CAN::attach(void (*fptr)(void), IrqType type) { + if (fptr) { + _irq[(CanIrqType)type].attach(fptr); + can_irq_set(&_can, (CanIrqType)type, 1); + } else { + can_irq_set(&_can, (CanIrqType)type, 0); + } +} + +void CAN::_irq_handler(uint32_t id, CanIrqType type) { + CAN *handler = (CAN*)id; + handler->_irq[type].call(); +} + +} // namespace mbed + +#endif diff --git a/common/CallChain.cpp b/common/CallChain.cpp new file mode 100644 index 0000000..e950903 --- /dev/null +++ b/common/CallChain.cpp @@ -0,0 +1,90 @@ +#include "CallChain.h" +#include "cmsis.h" + +namespace mbed { + +CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) { + _chain = new pFunctionPointer_t[size](); +} + +CallChain::~CallChain() { + clear(); + delete _chain; +} + +pFunctionPointer_t CallChain::add(void (*function)(void)) { + return common_add(new FunctionPointer(function)); +} + +pFunctionPointer_t CallChain::add_front(void (*function)(void)) { + return common_add_front(new FunctionPointer(function)); +} + +int CallChain::size() const { + return _elements; +} + +pFunctionPointer_t CallChain::get(int i) const { + if (i < 0 || i >= _elements) + return NULL; + return _chain[i]; +} + +int CallChain::find(pFunctionPointer_t f) const { + for (int i = 0; i < _elements; i++) + if (f == _chain[i]) + return i; + return -1; +} + +void CallChain::clear() { + for(int i = 0; i < _elements; i ++) { + delete _chain[i]; + _chain[i] = NULL; + } + _elements = 0; +} + +bool CallChain::remove(pFunctionPointer_t f) { + int i; + + if ((i = find(f)) == -1) + return false; + if (i != _elements - 1) + memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t)); + delete f; + _elements --; + return true; +} + +void CallChain::call() { + for(int i = 0; i < _elements; i++) + _chain[i]->call(); +} + +void CallChain::_check_size() { + if (_elements < _size) + return; + _size = (_size < 4) ? 4 : _size + 4; + pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size](); + memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t)); + delete _chain; + _chain = new_chain; +} + +pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) { + _check_size(); + _chain[_elements] = pf; + _elements ++; + return pf; +} + +pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) { + _check_size(); + memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t)); + _chain[0] = pf; + _elements ++; + return pf; +} + +} // namespace mbed diff --git a/common/Ethernet.cpp b/common/Ethernet.cpp new file mode 100644 index 0000000..279a88b --- /dev/null +++ b/common/Ethernet.cpp @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Ethernet.h" + +#if DEVICE_ETHERNET + +#include "ethernet_api.h" + +namespace mbed { + +Ethernet::Ethernet() { + ethernet_init(); +} + +Ethernet::~Ethernet() { + ethernet_free(); +} + +int Ethernet::write(const char *data, int size) { + return ethernet_write(data, size); +} + +int Ethernet::send() { + return ethernet_send(); +} + +int Ethernet::receive() { + return ethernet_receive(); +} + +int Ethernet::read(char *data, int size) { + return ethernet_read(data, size); +} + +void Ethernet::address(char *mac) { + return ethernet_address(mac); +} + +int Ethernet::link() { + return ethernet_link(); +} + +void Ethernet::set_link(Mode mode) { + int speed = -1; + int duplex = 0; + + switch(mode) { + case AutoNegotiate : speed = -1; duplex = 0; break; + case HalfDuplex10 : speed = 0; duplex = 0; break; + case FullDuplex10 : speed = 0; duplex = 1; break; + case HalfDuplex100 : speed = 1; duplex = 0; break; + case FullDuplex100 : speed = 1; duplex = 1; break; + } + + ethernet_set_link(speed, duplex); +} + +} // namespace mbed + +#endif diff --git a/common/FileBase.cpp b/common/FileBase.cpp new file mode 100644 index 0000000..fce113d --- /dev/null +++ b/common/FileBase.cpp @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "FileBase.h" + +namespace mbed { + +FileBase *FileBase::_head = NULL; + +FileBase::FileBase(const char *name, PathType t) : _next(NULL), + _name(name), + _path_type(t) { + if (name != NULL) { + // put this object at head of the list + _next = _head; + _head = this; + } else { + _next = NULL; + } +} + +FileBase::~FileBase() { + if (_name != NULL) { + // remove this object from the list + if (_head == this) { // first in the list, so just drop me + _head = _next; + } else { // find the object before me, then drop me + FileBase *p = _head; + while (p->_next != this) { + p = p->_next; + } + p->_next = _next; + } + } +} + +FileBase *FileBase::lookup(const char *name, unsigned int len) { + FileBase *p = _head; + while (p != NULL) { + /* Check that p->_name matches name and is the correct length */ + if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) { + return p; + } + p = p->_next; + } + return NULL; +} + +FileBase *FileBase::get(int n) { + FileBase *p = _head; + int m = 0; + while (p != NULL) { + if (m == n) return p; + + m++; + p = p->_next; + } + return NULL; +} + +const char* FileBase::getName(void) { + return _name; +} + +PathType FileBase::getPathType(void) { + return _path_type; +} + +} // namespace mbed + diff --git a/common/FileLike.cpp b/common/FileLike.cpp new file mode 100644 index 0000000..da13ead --- /dev/null +++ b/common/FileLike.cpp @@ -0,0 +1,28 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "FileLike.h" + +namespace mbed { + +FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) { + +} + +FileLike::~FileLike() { + +} + +} // namespace mbed diff --git a/common/FilePath.cpp b/common/FilePath.cpp new file mode 100644 index 0000000..09147a2 --- /dev/null +++ b/common/FilePath.cpp @@ -0,0 +1,76 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "FilePath.h" + +namespace mbed { + +FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) { + if ((file_path[0] != '/') || (file_path[1] == 0)) return; + + const char* file_system = &file_path[1]; + file_name = file_system; + int len = 0; + while (true) { + char c = *file_name; + if (c == '/') { // end of object name + file_name++; // point to one char after the '/' + break; + } + if (c == 0) { // end of object name, with no filename + break; + } + len++; + file_name++; + } + + fb = FileBase::lookup(file_system, len); +} + +const char* FilePath::fileName(void) { + return file_name; +} + +bool FilePath::isFileSystem(void) { + if (NULL == fb) + return false; + return (fb->getPathType() == FileSystemPathType); +} + +FileSystemLike* FilePath::fileSystem(void) { + if (isFileSystem()) { + return (FileSystemLike*)fb; + } + return NULL; +} + +bool FilePath::isFile(void) { + if (NULL == fb) + return false; + return (fb->getPathType() == FilePathType); +} + +FileLike* FilePath::file(void) { + if (isFile()) { + return (FileLike*)fb; + } + return NULL; +} + +bool FilePath::exists(void) { + return fb != NULL; +} + +} // namespace mbed diff --git a/common/FileSystemLike.cpp b/common/FileSystemLike.cpp new file mode 100644 index 0000000..df5d86d --- /dev/null +++ b/common/FileSystemLike.cpp @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "FileSystemLike.h" + +namespace mbed { + +class BaseDirHandle : public DirHandle { +public: + /* + We keep track of our current location as the n'th object in the + FileSystemLike list. Using a Base* instead would cause problems if that + object were to be destroyed between readdirs. + Using this method does mean though that destroying/creating objects can + give unusual results from readdir. + */ + off_t n; + struct dirent cur_entry; + + BaseDirHandle() : n(0), cur_entry() { + } + + virtual int closedir() { + delete this; + return 0; + } + + virtual struct dirent *readdir() { + FileBase *ptr = FileBase::get(n); + if (ptr == NULL) return NULL; + + /* Increment n, so next readdir gets the next item */ + n++; + + /* Setup cur entry and return a pointer to it */ + std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX); + return &cur_entry; + } + + virtual off_t telldir() { + return n; + } + + virtual void seekdir(off_t offset) { + n = offset; + } + + virtual void rewinddir() { + n = 0; + } +}; + +FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) { + +} + +FileSystemLike::~FileSystemLike() { + +} + +DirHandle *FileSystemLike::opendir() { + return new BaseDirHandle(); +} + +} // namespace mbed diff --git a/common/I2C.cpp b/common/I2C.cpp new file mode 100644 index 0000000..8806a5e --- /dev/null +++ b/common/I2C.cpp @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "I2C.h" + +#if DEVICE_I2C + +namespace mbed { + +I2C *I2C::_owner = NULL; + +I2C::I2C(PinName sda, PinName scl) : +#if DEVICE_I2C_ASYNCH + _irq(this), _usage(DMA_USAGE_NEVER), +#endif + _i2c(), _hz(100000) { + // The init function also set the frequency to 100000 + i2c_init(&_i2c, sda, scl); + + // Used to avoid unnecessary frequency updates + _owner = this; +} + +void I2C::frequency(int hz) { + _hz = hz; + + // We want to update the frequency even if we are already the bus owners + i2c_frequency(&_i2c, _hz); + + // Updating the frequency of the bus we become the owners of it + _owner = this; +} + +void I2C::aquire() { + if (_owner != this) { + i2c_frequency(&_i2c, _hz); + _owner = this; + } +} + +// write - Master Transmitter Mode +int I2C::write(int address, const char* data, int length, bool repeated) { + aquire(); + + int stop = (repeated) ? 0 : 1; + int written = i2c_write(&_i2c, address, data, length, stop); + + return length != written; +} + +int I2C::write(int data) { + return i2c_byte_write(&_i2c, data); +} + +// read - Master Reciever Mode +int I2C::read(int address, char* data, int length, bool repeated) { + aquire(); + + int stop = (repeated) ? 0 : 1; + int read = i2c_read(&_i2c, address, data, length, stop); + + return length != read; +} + +int I2C::read(int ack) { + if (ack) { + return i2c_byte_read(&_i2c, 0); + } else { + return i2c_byte_read(&_i2c, 1); + } +} + +void I2C::start(void) { + i2c_start(&_i2c); +} + +void I2C::stop(void) { + i2c_stop(&_i2c); +} + +#if DEVICE_I2C_ASYNCH + +int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event, bool repeated) +{ + if (i2c_active(&_i2c)) { + return -1; // transaction ongoing + } + aquire(); + + _callback = callback; + int stop = (repeated) ? 0 : 1; + _irq.callback(&I2C::irq_handler_asynch); + i2c_transfer_asynch(&_i2c, (void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length, address, stop, _irq.entry(), event, _usage); + return 0; +} + +void I2C::abort_transfer(void) +{ + i2c_abort_asynch(&_i2c); +} + +void I2C::irq_handler_asynch(void) +{ + int event = i2c_irq_handler_asynch(&_i2c); + if (_callback && event) { + _callback.call(event); + } + +} + + +#endif + +} // namespace mbed + +#endif diff --git a/common/I2CSlave.cpp b/common/I2CSlave.cpp new file mode 100644 index 0000000..4394093 --- /dev/null +++ b/common/I2CSlave.cpp @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "I2CSlave.h" + +#if DEVICE_I2CSLAVE + +namespace mbed { + +I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() { + i2c_init(&_i2c, sda, scl); + i2c_frequency(&_i2c, 100000); + i2c_slave_mode(&_i2c, 1); +} + +void I2CSlave::frequency(int hz) { + i2c_frequency(&_i2c, hz); +} + +void I2CSlave::address(int address) { + int addr = (address & 0xFF) | 1; + i2c_slave_address(&_i2c, 0, addr, 0); +} + +int I2CSlave::receive(void) { + return i2c_slave_receive(&_i2c); +} + +int I2CSlave::read(char *data, int length) { + return i2c_slave_read(&_i2c, data, length) != length; +} + +int I2CSlave::read(void) { + return i2c_byte_read(&_i2c, 0); +} + +int I2CSlave::write(const char *data, int length) { + return i2c_slave_write(&_i2c, data, length) != length; +} + +int I2CSlave::write(int data) { + return i2c_byte_write(&_i2c, data); +} + +void I2CSlave::stop(void) { + i2c_stop(&_i2c); +} + +} + +#endif diff --git a/common/InterruptIn.cpp b/common/InterruptIn.cpp new file mode 100644 index 0000000..8692124 --- /dev/null +++ b/common/InterruptIn.cpp @@ -0,0 +1,85 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "InterruptIn.h" + +#if DEVICE_INTERRUPTIN + +namespace mbed { + +InterruptIn::InterruptIn(PinName pin) : gpio(), + gpio_irq(), + _rise(), + _fall() { + gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this); + gpio_init_in(&gpio, pin); +} + +InterruptIn::~InterruptIn() { + gpio_irq_free(&gpio_irq); +} + +int InterruptIn::read() { + return gpio_read(&gpio); +} + +void InterruptIn::mode(PinMode pull) { + gpio_mode(&gpio, pull); +} + +void InterruptIn::rise(void (*fptr)(void)) { + if (fptr) { + _rise.attach(fptr); + gpio_irq_set(&gpio_irq, IRQ_RISE, 1); + } else { + gpio_irq_set(&gpio_irq, IRQ_RISE, 0); + } +} + +void InterruptIn::fall(void (*fptr)(void)) { + if (fptr) { + _fall.attach(fptr); + gpio_irq_set(&gpio_irq, IRQ_FALL, 1); + } else { + gpio_irq_set(&gpio_irq, IRQ_FALL, 0); + } +} + +void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) { + InterruptIn *handler = (InterruptIn*)id; + switch (event) { + case IRQ_RISE: handler->_rise.call(); break; + case IRQ_FALL: handler->_fall.call(); break; + case IRQ_NONE: break; + } +} + +void InterruptIn::enable_irq() { + gpio_irq_enable(&gpio_irq); +} + +void InterruptIn::disable_irq() { + gpio_irq_disable(&gpio_irq); +} + +#ifdef MBED_OPERATORS +InterruptIn::operator int() { + return read(); +} +#endif + +} // namespace mbed + +#endif diff --git a/common/InterruptManager.cpp b/common/InterruptManager.cpp new file mode 100644 index 0000000..e92fb68 --- /dev/null +++ b/common/InterruptManager.cpp @@ -0,0 +1,93 @@ +#include "cmsis.h" +#if defined(NVIC_NUM_VECTORS) + +#include "InterruptManager.h" +#include + +#define CHAIN_INITIAL_SIZE 4 + +namespace mbed { + +typedef void (*pvoidf)(void); + +InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL; + +InterruptManager* InterruptManager::get() { + if (NULL == _instance) + _instance = new InterruptManager(); + return _instance; +} + +InterruptManager::InterruptManager() { + memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*)); +} + +void InterruptManager::destroy() { + // Not a good idea to call this unless NO interrupt at all + // is under the control of the handler; otherwise, a system crash + // is very likely to occur + if (NULL != _instance) { + delete _instance; + _instance = (InterruptManager*)NULL; + } +} + +InterruptManager::~InterruptManager() { + for(int i = 0; i < NVIC_NUM_VECTORS; i++) + if (NULL != _chains[i]) + delete _chains[i]; +} + +bool InterruptManager::must_replace_vector(IRQn_Type irq) { + int irq_pos = get_irq_index(irq); + + if (NULL == _chains[irq_pos]) { + _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE); + _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq)); + return true; + } + return false; +} + +pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) { + int irq_pos = get_irq_index(irq); + bool change = must_replace_vector(irq); + + pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function); + if (change) + NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper); + return pf; +} + +bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) { + int irq_pos = get_irq_index(irq); + + if (NULL == _chains[irq_pos]) + return false; + if (!_chains[irq_pos]->remove(handler)) + return false; + // If there's a single function left in the chain, swith the interrupt vector + // to call that function directly. This way we save both time and space. + if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) { + NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function()); + delete _chains[irq_pos]; + _chains[irq_pos] = (CallChain*) NULL; + } + return true; +} + +void InterruptManager::irq_helper() { + _chains[__get_IPSR()]->call(); +} + +int InterruptManager::get_irq_index(IRQn_Type irq) { + return (int)irq + NVIC_USER_IRQ_OFFSET; +} + +void InterruptManager::static_irq_helper() { + InterruptManager::get()->irq_helper(); +} + +} // namespace mbed + +#endif diff --git a/common/LocalFileSystem.cpp b/common/LocalFileSystem.cpp new file mode 100644 index 0000000..9505d91 --- /dev/null +++ b/common/LocalFileSystem.cpp @@ -0,0 +1,223 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "LocalFileSystem.h" + +#if DEVICE_LOCALFILESYSTEM + +#include "semihost_api.h" +#include +#include + +namespace mbed { + +/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */ +typedef struct { + unsigned char hr; /* Hours [0..23] */ + unsigned char min; /* Minutes [0..59] */ + unsigned char sec; /* Seconds [0..59] */ + unsigned char day; /* Day [1..31] */ + unsigned char mon; /* Month [1..12] */ + unsigned short year; /* Year [1980..2107] */ +} FTIME; + +typedef struct { /* File Search info record */ + char name[32]; /* File name */ + long size; /* File size in bytes */ + int fileID; /* System File Identification */ + FTIME create_time; /* Date & time file was created */ + FTIME write_time; /* Date & time of last write */ +} XFINFO; + +#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */ +#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0) + +static int xffind (const char *pattern, XFINFO *info) { + unsigned param[4]; + + param[0] = (unsigned long)pattern; + param[1] = (unsigned long)strlen(pattern); + param[2] = (unsigned long)info; + param[3] = (unsigned long)sizeof(XFINFO); + + return __semihost(USR_XFFIND, param); +} + +#define OPEN_R 0 +#define OPEN_B 1 +#define OPEN_PLUS 2 +#define OPEN_W 4 +#define OPEN_A 8 +#define OPEN_INVALID -1 + +int posix_to_semihost_open_flags(int flags) { + /* POSIX flags -> semihosting open mode */ + int openmode; + if (flags & O_RDWR) { + /* a plus mode */ + openmode = OPEN_PLUS; + if (flags & O_APPEND) { + openmode |= OPEN_A; + } else if (flags & O_TRUNC) { + openmode |= OPEN_W; + } else { + openmode |= OPEN_R; + } + } else if (flags & O_WRONLY) { + /* write or append */ + if (flags & O_APPEND) { + openmode = OPEN_A; + } else { + openmode = OPEN_W; + } + } else if (flags == O_RDONLY) { + /* read mode */ + openmode = OPEN_R; + } else { + /* invalid flags */ + openmode = OPEN_INVALID; + } + + return openmode; +} + +FILEHANDLE local_file_open(const char* name, int flags) { + int openmode = posix_to_semihost_open_flags(flags); + if (openmode == OPEN_INVALID) { + return (FILEHANDLE)NULL; + } + + FILEHANDLE fh = semihost_open(name, openmode); + if (fh == -1) { + return (FILEHANDLE)NULL; + } + + return fh; +} + +LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) { +} + +int LocalFileHandle::close() { + int retval = semihost_close(_fh); + delete this; + return retval; +} + +ssize_t LocalFileHandle::write(const void *buffer, size_t length) { + ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written + n = length - n; // number of characters written + pos += n; + return n; +} + +ssize_t LocalFileHandle::read(void *buffer, size_t length) { + ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read + n = length - n; // number of characters read + pos += n; + return n; +} + +int LocalFileHandle::isatty() { + return semihost_istty(_fh); +} + +off_t LocalFileHandle::lseek(off_t position, int whence) { + if (whence == SEEK_CUR) { + position += pos; + } else if (whence == SEEK_END) { + position += semihost_flen(_fh); + } /* otherwise SEEK_SET, so position is fine */ + + /* Always seems to return -1, so just ignore for now. */ + semihost_seek(_fh, position); + pos = position; + return position; +} + +int LocalFileHandle::fsync() { + return semihost_ensure(_fh); +} + +off_t LocalFileHandle::flen() { + return semihost_flen(_fh); +} + +class LocalDirHandle : public DirHandle { + +public: + struct dirent cur_entry; + XFINFO info; + + LocalDirHandle() : cur_entry(), info() { + } + + virtual int closedir() { + delete this; + return 0; + } + + virtual struct dirent *readdir() { + if (xffind("*", &info)!=0) { + return NULL; + } + memcpy(cur_entry.d_name, info.name, sizeof(info.name)); + return &cur_entry; + } + + virtual void rewinddir() { + info.fileID = 0; + } + + virtual off_t telldir() { + return info.fileID; + } + + virtual void seekdir(off_t offset) { + info.fileID = offset; + } +}; + +FileHandle *LocalFileSystem::open(const char* name, int flags) { + /* reject filenames with / in them */ + for (const char *tmp = name; *tmp; tmp++) { + if (*tmp == '/') { + return NULL; + } + } + + int openmode = posix_to_semihost_open_flags(flags); + if (openmode == OPEN_INVALID) { + return NULL; + } + + FILEHANDLE fh = semihost_open(name, openmode); + if (fh == -1) { + return NULL; + } + return new LocalFileHandle(fh); +} + +int LocalFileSystem::remove(const char *filename) { + return semihost_remove(filename); +} + +DirHandle *LocalFileSystem::opendir(const char *name) { + return new LocalDirHandle(); +} + +} // namespace mbed + +#endif diff --git a/common/RawSerial.cpp b/common/RawSerial.cpp new file mode 100644 index 0000000..dc5db7a --- /dev/null +++ b/common/RawSerial.cpp @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "RawSerial.h" +#include "wait_api.h" +#include + +#if DEVICE_SERIAL + +#define STRING_STACK_LIMIT 120 + +namespace mbed { + +RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) { +} + +int RawSerial::getc() { + return _base_getc(); +} + +int RawSerial::putc(int c) { + return _base_putc(c); +} + +int RawSerial::puts(const char *str) { + while (*str) + putc(*str ++); + return 0; +} + +// Experimental support for printf in RawSerial. No Stream inheritance +// means we can't call printf() directly, so we use sprintf() instead. +// We only call malloc() for the sprintf() buffer if the buffer +// length is above a certain threshold, otherwise we use just the stack. +int RawSerial::printf(const char *format, ...) { + std::va_list arg; + va_start(arg, format); + int len = vsnprintf(NULL, 0, format, arg); + if (len < STRING_STACK_LIMIT) { + char temp[STRING_STACK_LIMIT]; + vsprintf(temp, format, arg); + puts(temp); + } else { + char *temp = new char[len + 1]; + vsprintf(temp, format, arg); + puts(temp); + delete[] temp; + } + va_end(arg); + return len; +} + +} // namespace mbed + +#endif diff --git a/common/SPI.cpp b/common/SPI.cpp new file mode 100644 index 0000000..e840470 --- /dev/null +++ b/common/SPI.cpp @@ -0,0 +1,180 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "SPI.h" + +#if DEVICE_SPI + +namespace mbed { + +#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI +CircularBuffer, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer; +#endif + +SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) : + _spi(), +#if DEVICE_SPI_ASYNCH + _irq(this), + _usage(DMA_USAGE_NEVER), +#endif + _bits(8), + _mode(0), + _hz(1000000) { + spi_init(&_spi, mosi, miso, sclk, ssel); + spi_format(&_spi, _bits, _mode, 0); + spi_frequency(&_spi, _hz); +} + +void SPI::format(int bits, int mode) { + _bits = bits; + _mode = mode; + SPI::_owner = NULL; // Not that elegant, but works. rmeyer + aquire(); +} + +void SPI::frequency(int hz) { + _hz = hz; + SPI::_owner = NULL; // Not that elegant, but works. rmeyer + aquire(); +} + +SPI* SPI::_owner = NULL; + +// ignore the fact there are multiple physical spis, and always update if it wasnt us last +void SPI::aquire() { + if (_owner != this) { + spi_format(&_spi, _bits, _mode, 0); + spi_frequency(&_spi, _hz); + _owner = this; + } +} + +int SPI::write(int value) { + aquire(); + return spi_master_write(&_spi, value); +} + +#if DEVICE_SPI_ASYNCH + +int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event) +{ + if (spi_active(&_spi)) { + return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event); + } + start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event); + return 0; +} + +void SPI::abort_transfer() +{ + spi_abort_asynch(&_spi); +#if TRANSACTION_QUEUE_SIZE_SPI + dequeue_transaction(); +#endif +} + + +void SPI::clear_transfer_buffer() +{ +#if TRANSACTION_QUEUE_SIZE_SPI + _transaction_buffer.reset(); +#endif +} + +void SPI::abort_all_transfers() +{ + clear_transfer_buffer(); + abort_transfer(); +} + +int SPI::set_dma_usage(DMAUsage usage) +{ + if (spi_active(&_spi)) { + return -1; + } + _usage = usage; + return 0; +} + +int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event) +{ +#if TRANSACTION_QUEUE_SIZE_SPI + transaction_t t; + + t.tx_buffer = const_cast(tx_buffer); + t.tx_length = tx_length; + t.rx_buffer = rx_buffer; + t.rx_length = rx_length; + t.event = event; + t.callback = callback; + t.width = bit_width; + Transaction transaction(this, t); + if (_transaction_buffer.full()) { + return -1; // the buffer is full + } else { + _transaction_buffer.push(transaction); + return 0; + } +#else + return -1; +#endif +} + +void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event) +{ + aquire(); + _callback = callback; + _irq.callback(&SPI::irq_handler_asynch); + spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage); +} + +#if TRANSACTION_QUEUE_SIZE_SPI + +void SPI::start_transaction(transaction_t *data) +{ + start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event); +} + +void SPI::dequeue_transaction() +{ + Transaction t; + if (_transaction_buffer.pop(t)) { + SPI* obj = t.get_object(); + transaction_t* data = t.get_transaction(); + obj->start_transaction(data); + } +} + +#endif + +void SPI::irq_handler_asynch(void) +{ + int event = spi_irq_handler_asynch(&_spi); + if (_callback && (event & SPI_EVENT_ALL)) { + _callback.call(event & SPI_EVENT_ALL); + } +#if TRANSACTION_QUEUE_SIZE_SPI + if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) { + // SPI peripheral is free (event happend), dequeue transaction + dequeue_transaction(); + } +#endif +} + +#endif + +} // namespace mbed + +#endif diff --git a/common/SPISlave.cpp b/common/SPISlave.cpp new file mode 100644 index 0000000..5e50316 --- /dev/null +++ b/common/SPISlave.cpp @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "SPISlave.h" + +#if DEVICE_SPISLAVE + +namespace mbed { + +SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) : + _spi(), + _bits(8), + _mode(0), + _hz(1000000) + { + spi_init(&_spi, mosi, miso, sclk, ssel); + spi_format(&_spi, _bits, _mode, 1); + spi_frequency(&_spi, _hz); +} + +void SPISlave::format(int bits, int mode) { + _bits = bits; + _mode = mode; + spi_format(&_spi, _bits, _mode, 1); +} + +void SPISlave::frequency(int hz) { + _hz = hz; + spi_frequency(&_spi, _hz); +} + +int SPISlave::receive(void) { + return(spi_slave_receive(&_spi)); +} + +int SPISlave::read(void) { + return(spi_slave_read(&_spi)); +} + +void SPISlave::reply(int value) { + spi_slave_write(&_spi, value); +} + +} // namespace mbed + +#endif diff --git a/common/Serial.cpp b/common/Serial.cpp new file mode 100644 index 0000000..602c87a --- /dev/null +++ b/common/Serial.cpp @@ -0,0 +1,36 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Serial.h" +#include "wait_api.h" + +#if DEVICE_SERIAL + +namespace mbed { + +Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) { +} + +int Serial::_getc() { + return _base_getc(); +} + +int Serial::_putc(int c) { + return _base_putc(c); +} + +} // namespace mbed + +#endif diff --git a/common/SerialBase.cpp b/common/SerialBase.cpp new file mode 100644 index 0000000..880a021 --- /dev/null +++ b/common/SerialBase.cpp @@ -0,0 +1,212 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "SerialBase.h" +#include "wait_api.h" + +#if DEVICE_SERIAL + +namespace mbed { + +SerialBase::SerialBase(PinName tx, PinName rx) : +#if DEVICE_SERIAL_ASYNCH + _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER), + _rx_usage(DMA_USAGE_NEVER), +#endif + _serial(), _baud(9600) { + serial_init(&_serial, tx, rx); + serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this); +} + +void SerialBase::baud(int baudrate) { + serial_baud(&_serial, baudrate); + _baud = baudrate; +} + +void SerialBase::format(int bits, Parity parity, int stop_bits) { + serial_format(&_serial, bits, (SerialParity)parity, stop_bits); +} + +int SerialBase::readable() { + return serial_readable(&_serial); +} + + +int SerialBase::writeable() { + return serial_writable(&_serial); +} + +void SerialBase::attach(void (*fptr)(void), IrqType type) { + if (fptr) { + _irq[type].attach(fptr); + serial_irq_set(&_serial, (SerialIrq)type, 1); + } else { + serial_irq_set(&_serial, (SerialIrq)type, 0); + } +} + +void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) { + SerialBase *handler = (SerialBase*)id; + handler->_irq[irq_type].call(); +} + +int SerialBase::_base_getc() { + return serial_getc(&_serial); +} + +int SerialBase::_base_putc(int c) { + serial_putc(&_serial, c); + return c; +} + +void SerialBase::send_break() { + // Wait for 1.5 frames before clearing the break condition + // This will have different effects on our platforms, but should + // ensure that we keep the break active for at least one frame. + // We consider a full frame (1 start bit + 8 data bits bits + + // 1 parity bit + 2 stop bits = 12 bits) for computation. + // One bit time (in us) = 1000000/_baud + // Twelve bits: 12000000/baud delay + // 1.5 frames: 18000000/baud delay + serial_break_set(&_serial); + wait_us(18000000/_baud); + serial_break_clear(&_serial); +} + +#if DEVICE_SERIAL_FC +void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) { + FlowControl flow_type = (FlowControl)type; + switch(type) { + case RTS: + serial_set_flow_control(&_serial, flow_type, flow1, NC); + break; + + case CTS: + serial_set_flow_control(&_serial, flow_type, NC, flow1); + break; + + case RTSCTS: + case Disabled: + serial_set_flow_control(&_serial, flow_type, flow1, flow2); + break; + + default: + break; + } +} +#endif + +#if DEVICE_SERIAL_ASYNCH + +int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t& callback, int event) +{ + if (serial_tx_active(&_serial)) { + return -1; // transaction ongoing + } + start_write((void *)buffer, length, 8, callback, event); + return 0; +} + +int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t& callback, int event) +{ + if (serial_tx_active(&_serial)) { + return -1; // transaction ongoing + } + start_write((void *)buffer, length, 16, callback, event); + return 0; +} + +void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event) +{ + _tx_callback = callback; + + _thunk_irq.callback(&SerialBase::interrupt_handler_asynch); + serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage); +} + +void SerialBase::abort_write(void) +{ + serial_tx_abort_asynch(&_serial); +} + +void SerialBase::abort_read(void) +{ + serial_rx_abort_asynch(&_serial); +} + +int SerialBase::set_dma_usage_tx(DMAUsage usage) +{ + if (serial_tx_active(&_serial)) { + return -1; + } + _tx_usage = usage; + return 0; +} + +int SerialBase::set_dma_usage_rx(DMAUsage usage) +{ + if (serial_tx_active(&_serial)) { + return -1; + } + _rx_usage = usage; + return 0; +} + +int SerialBase::read(uint8_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match) +{ + if (serial_rx_active(&_serial)) { + return -1; // transaction ongoing + } + start_read((void*)buffer, length, 8, callback, event, char_match); + return 0; +} + + +int SerialBase::read(uint16_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match) +{ + if (serial_rx_active(&_serial)) { + return -1; // transaction ongoing + } + start_read((void*)buffer, length, 16, callback, event, char_match); + return 0; +} + + +void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match) +{ + _rx_callback = callback; + _thunk_irq.callback(&SerialBase::interrupt_handler_asynch); + serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage); +} + +void SerialBase::interrupt_handler_asynch(void) +{ + int event = serial_irq_handler_asynch(&_serial); + int rx_event = event & SERIAL_EVENT_RX_MASK; + if (_rx_callback && rx_event) { + _rx_callback.call(rx_event); + } + + int tx_event = event & SERIAL_EVENT_TX_MASK; + if (_tx_callback && tx_event) { + _tx_callback.call(tx_event); + } +} + +#endif + +} // namespace mbed + +#endif diff --git a/common/Stream.cpp b/common/Stream.cpp new file mode 100644 index 0000000..6d3a335 --- /dev/null +++ b/common/Stream.cpp @@ -0,0 +1,111 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Stream.h" + +#include + +namespace mbed { + +Stream::Stream(const char *name) : FileLike(name), _file(NULL) { + /* open ourselves */ + char buf[12]; /* :0x12345678 + null byte */ + std::sprintf(buf, ":%p", this); + _file = std::fopen(buf, "w+"); + mbed_set_unbuffered_stream(_file); +} + +Stream::~Stream() { + fclose(_file); +} + +int Stream::putc(int c) { + fflush(_file); + return std::fputc(c, _file); +} +int Stream::puts(const char *s) { + fflush(_file); + return std::fputs(s, _file); +} +int Stream::getc() { + fflush(_file); + return mbed_getc(_file); +} +char* Stream::gets(char *s, int size) { + fflush(_file); + return mbed_gets(s,size,_file); +} + +int Stream::close() { + return 0; +} + +ssize_t Stream::write(const void* buffer, size_t length) { + const char* ptr = (const char*)buffer; + const char* end = ptr + length; + while (ptr != end) { + if (_putc(*ptr++) == EOF) { + break; + } + } + return ptr - (const char*)buffer; +} + +ssize_t Stream::read(void* buffer, size_t length) { + char* ptr = (char*)buffer; + char* end = ptr + length; + while (ptr != end) { + int c = _getc(); + if (c==EOF) break; + *ptr++ = c; + } + return ptr - (const char*)buffer; +} + +off_t Stream::lseek(off_t offset, int whence) { + return 0; +} + +int Stream::isatty() { + return 0; +} + +int Stream::fsync() { + return 0; +} + +off_t Stream::flen() { + return 0; +} + +int Stream::printf(const char* format, ...) { + std::va_list arg; + va_start(arg, format); + fflush(_file); + int r = vfprintf(_file, format, arg); + va_end(arg); + return r; +} + +int Stream::scanf(const char* format, ...) { + std::va_list arg; + va_start(arg, format); + fflush(_file); + int r = vfscanf(_file, format, arg); + va_end(arg); + return r; +} + +} // namespace mbed diff --git a/common/Ticker.cpp b/common/Ticker.cpp new file mode 100644 index 0000000..06abbb3 --- /dev/null +++ b/common/Ticker.cpp @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Ticker.h" + +#include "TimerEvent.h" +#include "FunctionPointer.h" +#include "ticker_api.h" + +namespace mbed { + +void Ticker::detach() { + remove(); + _function.attach(0); +} + +void Ticker::setup(timestamp_t t) { + remove(); + _delay = t; + insert(_delay + ticker_read(_ticker_data)); +} + +void Ticker::handler() { + insert(event.timestamp + _delay); + _function.call(); +} + +} // namespace mbed diff --git a/common/Timeout.cpp b/common/Timeout.cpp new file mode 100644 index 0000000..ed79502 --- /dev/null +++ b/common/Timeout.cpp @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Timeout.h" + +namespace mbed { + +void Timeout::handler() { + _function.call(); +} + +} // namespace mbed diff --git a/common/Timer.cpp b/common/Timer.cpp new file mode 100644 index 0000000..a084634 --- /dev/null +++ b/common/Timer.cpp @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Timer.h" +#include "ticker_api.h" +#include "us_ticker_api.h" + +namespace mbed { + +Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) { + reset(); +} + +Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) { + reset(); +} + +void Timer::start() { + if (!_running) { + _start = ticker_read(_ticker_data); + _running = 1; + } +} + +void Timer::stop() { + _time += slicetime(); + _running = 0; +} + +int Timer::read_us() { + return _time + slicetime(); +} + +float Timer::read() { + return (float)read_us() / 1000000.0f; +} + +int Timer::read_ms() { + return read_us() / 1000; +} + +int Timer::slicetime() { + if (_running) { + return ticker_read(_ticker_data) - _start; + } else { + return 0; + } +} + +void Timer::reset() { + _start = ticker_read(_ticker_data); + _time = 0; +} + +#ifdef MBED_OPERATORS +Timer::operator float() { + return read(); +} +#endif + +} // namespace mbed diff --git a/common/TimerEvent.cpp b/common/TimerEvent.cpp new file mode 100644 index 0000000..4c7481f --- /dev/null +++ b/common/TimerEvent.cpp @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "TimerEvent.h" +#include "cmsis.h" + +#include +#include "ticker_api.h" +#include "us_ticker_api.h" + +namespace mbed { + +TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data()) { + ticker_set_handler(_ticker_data, (&TimerEvent::irq)); +} + +TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) { + ticker_set_handler(_ticker_data, (&TimerEvent::irq)); +} + +void TimerEvent::irq(uint32_t id) { + TimerEvent *timer_event = (TimerEvent*)id; + timer_event->handler(); +} + +TimerEvent::~TimerEvent() { + remove(); +} + +// insert in to linked list +void TimerEvent::insert(timestamp_t timestamp) { + ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this); +} + +void TimerEvent::remove() { + ticker_remove_event(_ticker_data, &event); +} + +} // namespace mbed diff --git a/common/assert.c b/common/assert.c new file mode 100644 index 0000000..3d2097c --- /dev/null +++ b/common/assert.c @@ -0,0 +1,22 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" + +void mbed_assert_internal(const char *expr, const char *file, int line) +{ + error("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line); +} diff --git a/common/board.c b/common/board.c new file mode 100644 index 0000000..9103236 --- /dev/null +++ b/common/board.c @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "wait_api.h" +#include "toolchain.h" +#include "mbed_interface.h" + +WEAK void mbed_die(void) { +#ifndef NRF51_H + __disable_irq(); // dont allow interrupts to disturb the flash pattern +#endif +#if (DEVICE_ERROR_RED == 1) + gpio_t led_red; gpio_init_out(&led_red, LED_RED); +#elif (DEVICE_ERROR_PATTERN == 1) + gpio_t led_1; gpio_init_out(&led_1, LED1); + gpio_t led_2; gpio_init_out(&led_2, LED2); + gpio_t led_3; gpio_init_out(&led_3, LED3); + gpio_t led_4; gpio_init_out(&led_4, LED4); +#endif + + while (1) { +#if (DEVICE_ERROR_RED == 1) + gpio_write(&led_red, 1); + +#elif (DEVICE_ERROR_PATTERN == 1) + gpio_write(&led_1, 1); + gpio_write(&led_2, 0); + gpio_write(&led_3, 0); + gpio_write(&led_4, 1); +#endif + + wait_ms(150); + +#if (DEVICE_ERROR_RED == 1) + gpio_write(&led_red, 0); + +#elif (DEVICE_ERROR_PATTERN == 1) + gpio_write(&led_1, 0); + gpio_write(&led_2, 1); + gpio_write(&led_3, 1); + gpio_write(&led_4, 0); +#endif + + wait_ms(150); + } +} diff --git a/common/error.c b/common/error.c new file mode 100644 index 0000000..b307d87 --- /dev/null +++ b/common/error.c @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include "device.h" +#include "toolchain.h" +#include "mbed_error.h" +#if DEVICE_STDIO_MESSAGES +#include +#endif + +WEAK void error(const char* format, ...) { +#if DEVICE_STDIO_MESSAGES + va_list arg; + va_start(arg, format); + vfprintf(stderr, format, arg); + va_end(arg); +#endif + exit(1); +} diff --git a/common/gpio.c b/common/gpio.c new file mode 100644 index 0000000..3839e8b --- /dev/null +++ b/common/gpio.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" + +static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode) +{ + gpio_init(gpio, pin); + if (pin != NC) { + gpio_dir(gpio, PIN_INPUT); + gpio_mode(gpio, mode); + } +} + +static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value) +{ + gpio_init(gpio, pin); + if (pin != NC) { + gpio_write(gpio, value); + gpio_dir(gpio, PIN_OUTPUT); + gpio_mode(gpio, mode); + } +} + +void gpio_init_in(gpio_t* gpio, PinName pin) { + gpio_init_in_ex(gpio, pin, PullDefault); +} + +void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) { + _gpio_init_in(gpio, pin, mode); +} + +void gpio_init_out(gpio_t* gpio, PinName pin) { + gpio_init_out_ex(gpio, pin, 0); +} + +void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) { + _gpio_init_out(gpio, pin, PullNone, value); +} + +void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) { + if (direction == PIN_INPUT) { + _gpio_init_in(gpio, pin, mode); + if (pin != NC) + gpio_write(gpio, value); // we prepare the value in case it is switched later + } else { + _gpio_init_out(gpio, pin, mode, value); + } +} diff --git a/common/lp_ticker_api.c b/common/lp_ticker_api.c new file mode 100644 index 0000000..ab0a531 --- /dev/null +++ b/common/lp_ticker_api.c @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "lp_ticker_api.h" + +#if DEVICE_LOWPOWERTIMER + +static ticker_event_queue_t events; + +static const ticker_interface_t lp_interface = { + .init = lp_ticker_init, + .read = lp_ticker_read, + .disable_interrupt = lp_ticker_disable_interrupt, + .clear_interrupt = lp_ticker_clear_interrupt, + .set_interrupt = lp_ticker_set_interrupt, +}; + +static const ticker_data_t lp_data = { + .interface = &lp_interface, + .queue = &events, +}; + +const ticker_data_t* get_lp_ticker_data(void) +{ + return &lp_data; +} + +void lp_ticker_irq_handler(void) +{ + ticker_irq_handler(&lp_data); +} + +#endif diff --git a/common/mbed_interface.c b/common/mbed_interface.c new file mode 100644 index 0000000..5b27b30 --- /dev/null +++ b/common/mbed_interface.c @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_interface.h" + +#include "gpio_api.h" +#include "wait_api.h" +#include "semihost_api.h" +#include "mbed_error.h" +#include "toolchain.h" + +#if DEVICE_SEMIHOST + +// return true if a debugger is attached, indicating mbed interface is connected +int mbed_interface_connected(void) { + return semihost_connected(); +} + +int mbed_interface_reset(void) { + if (mbed_interface_connected()) { + semihost_reset(); + return 0; + } else { + return -1; + } +} + +WEAK int mbed_interface_uid(char *uid) { + if (mbed_interface_connected()) { + return semihost_uid(uid); // Returns 0 if successful, -1 on failure + } else { + uid[0] = 0; + return -1; + } +} + +int mbed_interface_disconnect(void) { + int res; + if (mbed_interface_connected()) { + if ((res = semihost_disabledebug()) != 0) + return res; + while (mbed_interface_connected()); + return 0; + } else { + return -1; + } +} + +int mbed_interface_powerdown(void) { + int res; + if (mbed_interface_connected()) { + if ((res = semihost_powerdown()) != 0) + return res; + while (mbed_interface_connected()); + return 0; + } else { + return -1; + } +} + +// for backward compatibility +void mbed_reset(void) { + mbed_interface_reset(); +} + +WEAK int mbed_uid(char *uid) { + return mbed_interface_uid(uid); +} +#endif + +WEAK void mbed_mac_address(char *mac) { +#if DEVICE_SEMIHOST + char uid[DEVICE_ID_LENGTH + 1]; + int i; + + // if we have a UID, extract the MAC + if (mbed_interface_uid(uid) == 0) { + char *p = uid; +#if defined(DEVICE_MAC_OFFSET) + p += DEVICE_MAC_OFFSET; +#endif + for (i=0; i<6; i++) { + int byte; + sscanf(p, "%2x", &byte); + mac[i] = byte; + p += 2; + } + mac[0] &= ~0x01; // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b) + } else { // else return a default MAC +#endif + mac[0] = 0x00; + mac[1] = 0x02; + mac[2] = 0xF7; + mac[3] = 0xF0; + mac[4] = 0x00; + mac[5] = 0x00; +#if DEVICE_SEMIHOST + } +#endif +} diff --git a/common/pinmap_common.c b/common/pinmap_common.c new file mode 100644 index 0000000..5aab0e6 --- /dev/null +++ b/common/pinmap_common.c @@ -0,0 +1,89 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pinmap.h" +#include "mbed_error.h" + +void pinmap_pinout(PinName pin, const PinMap *map) { + if (pin == NC) + return; + + while (map->pin != NC) { + if (map->pin == pin) { + pin_function(pin, map->function); + + pin_mode(pin, PullNone); + return; + } + map++; + } + error("could not pinout"); +} + +uint32_t pinmap_merge(uint32_t a, uint32_t b) { + // both are the same (inc both NC) + if (a == b) + return a; + + // one (or both) is not connected + if (a == (uint32_t)NC) + return b; + if (b == (uint32_t)NC) + return a; + + // mis-match error case + error("pinmap mis-match"); + return (uint32_t)NC; +} + +uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) { + while (map->pin != NC) { + if (map->pin == pin) + return map->peripheral; + map++; + } + return (uint32_t)NC; +} + +uint32_t pinmap_peripheral(PinName pin, const PinMap* map) { + uint32_t peripheral = (uint32_t)NC; + + if (pin == (PinName)NC) + return (uint32_t)NC; + peripheral = pinmap_find_peripheral(pin, map); + if ((uint32_t)NC == peripheral) // no mapping available + error("pinmap not found for peripheral"); + return peripheral; +} + +uint32_t pinmap_find_function(PinName pin, const PinMap* map) { + while (map->pin != NC) { + if (map->pin == pin) + return map->function; + map++; + } + return (uint32_t)NC; +} + +uint32_t pinmap_function(PinName pin, const PinMap* map) { + uint32_t function = (uint32_t)NC; + + if (pin == (PinName)NC) + return (uint32_t)NC; + function = pinmap_find_function(pin, map); + if ((uint32_t)NC == function) // no mapping available + error("pinmap not found for function"); + return function; +} diff --git a/common/retarget.cpp b/common/retarget.cpp new file mode 100644 index 0000000..82411ab --- /dev/null +++ b/common/retarget.cpp @@ -0,0 +1,569 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "platform.h" +#include "FileHandle.h" +#include "FileSystemLike.h" +#include "FilePath.h" +#include "serial_api.h" +#include "toolchain.h" +#include "semihost_api.h" +#include "mbed_interface.h" +#if DEVICE_STDIO_MESSAGES +#include +#endif +#include + +#if defined(__ARMCC_VERSION) +# include +# define PREFIX(x) _sys##x +# define OPEN_MAX _SYS_OPEN +# ifdef __MICROLIB +# pragma import(__use_full_stdio) +# endif + +#elif defined(__ICCARM__) +# include +# define PREFIX(x) _##x +# define OPEN_MAX 16 + +# define STDIN_FILENO 0 +# define STDOUT_FILENO 1 +# define STDERR_FILENO 2 + +#else +# include +# include +# include +# define PREFIX(x) x +#endif + +using namespace mbed; + +#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000) +// Before version 5.03, we were using a patched version of microlib with proper names +extern const char __stdin_name[] = ":tt"; +extern const char __stdout_name[] = ":tt"; +extern const char __stderr_name[] = ":tt"; + +#else +extern const char __stdin_name[] = "/stdin"; +extern const char __stdout_name[] = "/stdout"; +extern const char __stderr_name[] = "/stderr"; +#endif + +/* newlib has the filehandle field in the FILE struct as a short, so + * we can't just return a Filehandle* from _open and instead have to + * put it in a filehandles array and return the index into that array + * (or rather index+3, as filehandles 0-2 are stdin/out/err). + */ +static FileHandle *filehandles[OPEN_MAX]; + +FileHandle::~FileHandle() { + /* Remove all open filehandles for this */ + for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) { + if (filehandles[fh_i] == this) { + filehandles[fh_i] = NULL; + } + } +} + +#if DEVICE_SERIAL +extern int stdio_uart_inited; +extern serial_t stdio_uart; +#endif + +static void init_serial() { +#if DEVICE_SERIAL + if (stdio_uart_inited) return; + serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX); +#endif +} + +static inline int openmode_to_posix(int openmode) { + int posix = openmode; +#ifdef __ARMCC_VERSION + if (openmode & OPEN_PLUS) { + posix = O_RDWR; + } else if(openmode & OPEN_W) { + posix = O_WRONLY; + } else if(openmode & OPEN_A) { + posix = O_WRONLY|O_APPEND; + } else { + posix = O_RDONLY; + } + /* a, w, a+, w+ all create if file does not already exist */ + if (openmode & (OPEN_A|OPEN_W)) { + posix |= O_CREAT; + } + /* w and w+ truncate */ + if (openmode & OPEN_W) { + posix |= O_TRUNC; + } +#elif defined(__ICCARM__) + switch (openmode & _LLIO_RDWRMASK) { + case _LLIO_RDONLY: posix = O_RDONLY; break; + case _LLIO_WRONLY: posix = O_WRONLY; break; + case _LLIO_RDWR : posix = O_RDWR ; break; + } + if (openmode & _LLIO_CREAT ) posix |= O_CREAT; + if (openmode & _LLIO_APPEND) posix |= O_APPEND; + if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC; +#endif + return posix; +} + +extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) { + #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000) + // Before version 5.03, we were using a patched version of microlib with proper names + // This is the workaround that the microlib author suggested us + static int n = 0; + if (!std::strcmp(name, ":tt")) return n++; + + #else + /* Use the posix convention that stdin,out,err are filehandles 0,1,2. + */ + if (std::strcmp(name, __stdin_name) == 0) { + init_serial(); + return 0; + } else if (std::strcmp(name, __stdout_name) == 0) { + init_serial(); + return 1; + } else if (std::strcmp(name, __stderr_name) == 0) { + init_serial(); + return 2; + } + #endif + + // find the first empty slot in filehandles + unsigned int fh_i; + for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) { + if (filehandles[fh_i] == NULL) break; + } + if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) { + return -1; + } + + FileHandle *res; + + /* FILENAME: ":0x12345678" describes a FileLike* */ + if (name[0] == ':') { + void *p; + sscanf(name, ":%p", &p); + res = (FileHandle*)p; + + /* FILENAME: "/file_system/file_name" */ + } else { + FilePath path(name); + + if (!path.exists()) + return -1; + else if (path.isFile()) { + res = path.file(); + } else { + FileSystemLike *fs = path.fileSystem(); + if (fs == NULL) return -1; + int posix_mode = openmode_to_posix(openmode); + res = fs->open(path.fileName(), posix_mode); /* NULL if fails */ + } + } + + if (res == NULL) return -1; + filehandles[fh_i] = res; + + return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err +} + +extern "C" int PREFIX(_close)(FILEHANDLE fh) { + if (fh < 3) return 0; + + FileHandle* fhc = filehandles[fh-3]; + filehandles[fh-3] = NULL; + if (fhc == NULL) return -1; + + return fhc->close(); +} + +#if defined(__ICCARM__) +extern "C" size_t __write (int fh, const unsigned char *buffer, size_t length) { +#else +extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) { +#endif + int n; // n is the number of bytes written + if (fh < 3) { +#if DEVICE_SERIAL + if (!stdio_uart_inited) init_serial(); + for (unsigned int i = 0; i < length; i++) { + serial_putc(&stdio_uart, buffer[i]); + } +#endif + n = length; + } else { + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) return -1; + + n = fhc->write(buffer, length); + } +#ifdef __ARMCC_VERSION + return length-n; +#else + return n; +#endif +} + +#if defined(__ICCARM__) +extern "C" size_t __read (int fh, unsigned char *buffer, size_t length) { +#else +extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) { +#endif + int n; // n is the number of bytes read + if (fh < 3) { + // only read a character at a time from stdin +#if DEVICE_SERIAL + if (!stdio_uart_inited) init_serial(); + *buffer = serial_getc(&stdio_uart); +#endif + n = 1; + } else { + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) return -1; + + n = fhc->read(buffer, length); + } +#ifdef __ARMCC_VERSION + return length-n; +#else + return n; +#endif +} + +#ifdef __ARMCC_VERSION +extern "C" int PREFIX(_istty)(FILEHANDLE fh) +#else +extern "C" int _isatty(FILEHANDLE fh) +#endif +{ + /* stdin, stdout and stderr should be tty */ + if (fh < 3) return 1; + + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) return -1; + + return fhc->isatty(); +} + +extern "C" +#if defined(__ARMCC_VERSION) +int _sys_seek(FILEHANDLE fh, long position) +#elif defined(__ICCARM__) +long __lseek(int fh, long offset, int whence) +#else +int _lseek(FILEHANDLE fh, int offset, int whence) +#endif +{ + if (fh < 3) return 0; + + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) return -1; + +#if defined(__ARMCC_VERSION) + return fhc->lseek(position, SEEK_SET); +#else + return fhc->lseek(offset, whence); +#endif +} + +#ifdef __ARMCC_VERSION +extern "C" int PREFIX(_ensure)(FILEHANDLE fh) { + if (fh < 3) return 0; + + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) return -1; + + return fhc->fsync(); +} + +extern "C" long PREFIX(_flen)(FILEHANDLE fh) { + if (fh < 3) return 0; + + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) return -1; + + return fhc->flen(); +} +#endif + + +#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__) +extern "C" int _fstat(int fd, struct stat *st) { + if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) { + st->st_mode = S_IFCHR; + return 0; + } + + errno = EBADF; + return -1; +} +#endif + +namespace std { +extern "C" int remove(const char *path) { + FilePath fp(path); + FileSystemLike *fs = fp.fileSystem(); + if (fs == NULL) return -1; + + return fs->remove(fp.fileName()); +} + +extern "C" int rename(const char *oldname, const char *newname) { + FilePath fpOld(oldname); + FilePath fpNew(newname); + FileSystemLike *fsOld = fpOld.fileSystem(); + FileSystemLike *fsNew = fpNew.fileSystem(); + + /* rename only if both files are on the same FS */ + if (fsOld != fsNew || fsOld == NULL) return -1; + + return fsOld->rename(fpOld.fileName(), fpNew.fileName()); +} + +extern "C" char *tmpnam(char *s) { + return NULL; +} + +extern "C" FILE *tmpfile() { + return NULL; +} +} // namespace std + +#ifdef __ARMCC_VERSION +extern "C" char *_sys_command_string(char *cmd, int len) { + return NULL; +} +#endif + +extern "C" DIR *opendir(const char *path) { + /* root dir is FileSystemLike */ + if (path[0] == '/' && path[1] == 0) { + return FileSystemLike::opendir(); + } + + FilePath fp(path); + FileSystemLike* fs = fp.fileSystem(); + if (fs == NULL) return NULL; + + return fs->opendir(fp.fileName()); +} + +extern "C" struct dirent *readdir(DIR *dir) { + return dir->readdir(); +} + +extern "C" int closedir(DIR *dir) { + return dir->closedir(); +} + +extern "C" void rewinddir(DIR *dir) { + dir->rewinddir(); +} + +extern "C" off_t telldir(DIR *dir) { + return dir->telldir(); +} + +extern "C" void seekdir(DIR *dir, off_t off) { + dir->seekdir(off); +} + +extern "C" int mkdir(const char *path, mode_t mode) { + FilePath fp(path); + FileSystemLike *fs = fp.fileSystem(); + if (fs == NULL) return -1; + + return fs->mkdir(fp.fileName(), mode); +} + +#if defined(TOOLCHAIN_GCC) +/* prevents the exception handling name demangling code getting pulled in */ +#include "mbed_error.h" +namespace __gnu_cxx { + void __verbose_terminate_handler() { + error("Exception"); + } +} +extern "C" WEAK void __cxa_pure_virtual(void); +extern "C" WEAK void __cxa_pure_virtual(void) { + exit(1); +} + +#endif + +// **************************************************************************** +// mbed_main is a function that is called before main() +// mbed_sdk_init() is also a function that is called before main(), but unlike +// mbed_main(), it is not meant for user code, but for the SDK itself to perform +// initializations before main() is called. + +extern "C" WEAK void mbed_main(void); +extern "C" WEAK void mbed_main(void) { +} + +extern "C" WEAK void mbed_sdk_init(void); +extern "C" WEAK void mbed_sdk_init(void) { +} + +#if defined(TOOLCHAIN_ARM) +extern "C" int $Super$$main(void); + +extern "C" int $Sub$$main(void) { + mbed_sdk_init(); + mbed_main(); + return $Super$$main(); +} +#elif defined(TOOLCHAIN_GCC) +extern "C" int __real_main(void); + +extern "C" int __wrap_main(void) { + mbed_sdk_init(); + mbed_main(); + return __real_main(); +} +#elif defined(TOOLCHAIN_IAR) +// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent +// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting +// 'main' to another symbol looses the original 'main' symbol. However, its startup +// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined. +// Since mbed doesn't use argc/argv, we use this function to call our mbed_main. +extern "C" void __iar_argc_argv() { + mbed_sdk_init(); + mbed_main(); +} +#endif + +// Provide implementation of _sbrk (low-level dynamic memory allocation +// routine) for GCC_ARM which compares new heap pointer with MSP instead of +// SP. This make it compatible with RTX RTOS thread stacks. +#if defined(TOOLCHAIN_GCC_ARM) +// Linker defined symbol used by _sbrk to indicate where heap should start. +extern "C" int __end__; + +#if defined(TARGET_CORTEX_A) +extern "C" uint32_t __HeapLimit; +#endif + +// Turn off the errno macro and use actual global variable instead. +#undef errno +extern "C" int errno; + +// For ARM7 only +register unsigned char * stack_ptr __asm ("sp"); + +// Dynamic memory allocation related syscall. +extern "C" caddr_t _sbrk(int incr) { + static unsigned char* heap = (unsigned char*)&__end__; + unsigned char* prev_heap = heap; + unsigned char* new_heap = heap + incr; + +#if defined(TARGET_ARM7) + if (new_heap >= stack_ptr) { +#elif defined(TARGET_CORTEX_A) + if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */ +#else + if (new_heap >= (unsigned char*)__get_MSP()) { +#endif + errno = ENOMEM; + return (caddr_t)-1; + } + + heap = new_heap; + return (caddr_t) prev_heap; +} +#endif + + +#ifdef TOOLCHAIN_GCC_CW +// TODO: Ideally, we would like to define directly "_ExitProcess" +extern "C" void mbed_exit(int return_code) { +#elif defined TOOLCHAIN_GCC_ARM +extern "C" void _exit(int return_code) { +#else +namespace std { +extern "C" void exit(int return_code) { +#endif + +#if DEVICE_STDIO_MESSAGES + fflush(stdout); + fflush(stderr); +#endif + +#if DEVICE_SEMIHOST + if (mbed_interface_connected()) { + semihost_exit(); + } +#endif + if (return_code) { + mbed_die(); + } + + while (1); +} + +#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW) +} //namespace std +#endif + + +namespace mbed { + +void mbed_set_unbuffered_stream(FILE *_file) { +#if defined (__ICCARM__) + char buf[2]; + std::setvbuf(_file,buf,_IONBF,NULL); +#else + setbuf(_file, NULL); +#endif +} + +int mbed_getc(FILE *_file){ +#if defined (__ICCARM__) + /*This is only valid for unbuffered streams*/ + int res = std::fgetc(_file); + if (res>=0){ + _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */ + _file->_Rend = _file->_Wend; + _file->_Next = _file->_Wend; + } + return res; +#else + return std::fgetc(_file); +#endif +} + +char* mbed_gets(char*s, int size, FILE *_file){ +#if defined (__ICCARM__) + /*This is only valid for unbuffered streams*/ + char *str = fgets(s,size,_file); + if (str!=NULL){ + _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */ + _file->_Rend = _file->_Wend; + _file->_Next = _file->_Wend; + } + return str; +#else + return std::fgets(s,size,_file); +#endif +} + +} // namespace mbed diff --git a/common/rtc_time.c b/common/rtc_time.c new file mode 100644 index 0000000..9822797 --- /dev/null +++ b/common/rtc_time.c @@ -0,0 +1,89 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" + +#include +#include "rtc_time.h" +#include "us_ticker_api.h" + +#if DEVICE_RTC +static void (*_rtc_init)(void) = rtc_init; +static int (*_rtc_isenabled)(void) = rtc_isenabled; +static time_t (*_rtc_read)(void) = rtc_read; +static void (*_rtc_write)(time_t t) = rtc_write; +#else +static void (*_rtc_init)(void) = NULL; +static int (*_rtc_isenabled)(void) = NULL; +static time_t (*_rtc_read)(void) = NULL; +static void (*_rtc_write)(time_t t) = NULL; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#if defined (__ICCARM__) +time_t __time32(time_t *timer) +#else +time_t time(time_t *timer) +#endif + +{ + if (_rtc_isenabled != NULL) { + if (!(_rtc_isenabled())) { + set_time(0); + } + } + + time_t t = 0; + if (_rtc_read != NULL) { + t = _rtc_read(); + } + + if (timer != NULL) { + *timer = t; + } + return t; +} + +void set_time(time_t t) { + if (_rtc_init != NULL) { + _rtc_init(); + } + if (_rtc_write != NULL) { + _rtc_write(t); + } +} + +clock_t clock() { + clock_t t = us_ticker_read(); + t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time + return t; +} + +void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) { + __disable_irq(); + _rtc_read = read_rtc; + _rtc_write = write_rtc; + _rtc_init = init_rtc; + _rtc_isenabled = isenabled_rtc; + __enable_irq(); +} + + + +#ifdef __cplusplus +} +#endif diff --git a/common/semihost_api.c b/common/semihost_api.c new file mode 100644 index 0000000..e4e136e --- /dev/null +++ b/common/semihost_api.c @@ -0,0 +1,162 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis.h" +#include "semihost_api.h" + +#include +#include + +#if DEVICE_SEMIHOST + +// ARM Semihosting Commands +#define SYS_OPEN (0x1) +#define SYS_CLOSE (0x2) +#define SYS_WRITE (0x5) +#define SYS_READ (0x6) +#define SYS_ISTTY (0x9) +#define SYS_SEEK (0xa) +#define SYS_ENSURE (0xb) +#define SYS_FLEN (0xc) +#define SYS_REMOVE (0xe) +#define SYS_RENAME (0xf) +#define SYS_EXIT (0x18) + +// mbed Semihosting Commands +#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff +#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0) +#define USR_UID (RESERVED_FOR_USER_APPLICATIONS + 1) +#define USR_RESET (RESERVED_FOR_USER_APPLICATIONS + 2) +#define USR_VBUS (RESERVED_FOR_USER_APPLICATIONS + 3) +#define USR_POWERDOWN (RESERVED_FOR_USER_APPLICATIONS + 4) +#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5) + +#if DEVICE_LOCALFILESYSTEM +FILEHANDLE semihost_open(const char* name, int openmode) { + uint32_t args[3]; + args[0] = (uint32_t)name; + args[1] = (uint32_t)openmode; + args[2] = (uint32_t)strlen(name); + return __semihost(SYS_OPEN, args); +} + +int semihost_close(FILEHANDLE fh) { + return __semihost(SYS_CLOSE, &fh); +} + +int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) { + if (length == 0) return 0; + + uint32_t args[3]; + args[0] = (uint32_t)fh; + args[1] = (uint32_t)buffer; + args[2] = (uint32_t)length; + return __semihost(SYS_WRITE, args); +} + +int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) { + uint32_t args[3]; + args[0] = (uint32_t)fh; + args[1] = (uint32_t)buffer; + args[2] = (uint32_t)length; + return __semihost(SYS_READ, args); +} + +int semihost_istty(FILEHANDLE fh) { + return __semihost(SYS_ISTTY, &fh); +} + +int semihost_seek(FILEHANDLE fh, long position) { + uint32_t args[2]; + args[0] = (uint32_t)fh; + args[1] = (uint32_t)position; + return __semihost(SYS_SEEK, args); +} + +int semihost_ensure(FILEHANDLE fh) { + return __semihost(SYS_ENSURE, &fh); +} + +long semihost_flen(FILEHANDLE fh) { + return __semihost(SYS_FLEN, &fh); +} + +int semihost_remove(const char *name) { + uint32_t args[2]; + args[0] = (uint32_t)name; + args[1] = (uint32_t)strlen(name); + return __semihost(SYS_REMOVE, args); +} + +int semihost_rename(const char *old_name, const char *new_name) { + uint32_t args[4]; + args[0] = (uint32_t)old_name; + args[1] = (uint32_t)strlen(old_name); + args[0] = (uint32_t)new_name; + args[1] = (uint32_t)strlen(new_name); + return __semihost(SYS_RENAME, args); +} +#endif + +int semihost_exit(void) { + uint32_t args[4]; + return __semihost(SYS_EXIT, args); +} + +int semihost_uid(char *uid) { + uint32_t args[2]; + args[0] = (uint32_t)uid; + args[1] = DEVICE_ID_LENGTH + 1; + return __semihost(USR_UID, &args); +} + +int semihost_reset(void) { + // Does not normally return, however if used with older firmware versions + // that do not support this call it will return -1. + return __semihost(USR_RESET, NULL); +} + +int semihost_vbus(void) { + return __semihost(USR_VBUS, NULL); +} + +int semihost_powerdown(void) { + return __semihost(USR_POWERDOWN, NULL); +} + +#if DEVICE_DEBUG_AWARENESS + +int semihost_connected(void) { + return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0; +} + +#else +// These processors cannot know if the interface is connect, assume so: +static int is_debugger_attached = 1; + +int semihost_connected(void) { + return is_debugger_attached; +} +#endif + +int semihost_disabledebug(void) { +#if !(DEVICE_DEBUG_AWARENESS) + is_debugger_attached = 0; +#endif + return __semihost(USR_DISABLEDEBUG, NULL); +} + +#endif + diff --git a/common/ticker_api.c b/common/ticker_api.c new file mode 100644 index 0000000..52b4888 --- /dev/null +++ b/common/ticker_api.c @@ -0,0 +1,135 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "ticker_api.h" +#include "cmsis.h" + +void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler) { + data->interface->init(); + + data->queue->event_handler = handler; +} + +void ticker_irq_handler(const ticker_data_t *const data) { + data->interface->clear_interrupt(); + + /* Go through all the pending TimerEvents */ + while (1) { + if (data->queue->head == NULL) { + // There are no more TimerEvents left, so disable matches. + data->interface->disable_interrupt(); + return; + } + + if ((int)(data->queue->head->timestamp - data->interface->read()) <= 0) { + // This event was in the past: + // point to the following one and execute its handler + ticker_event_t *p = data->queue->head; + data->queue->head = data->queue->head->next; + if (data->queue->event_handler != NULL) { + (*data->queue->event_handler)(p->id); // NOTE: the handler can set new events + } + /* Note: We continue back to examining the head because calling the + * event handler may have altered the chain of pending events. */ + } else { + // This event and the following ones in the list are in the future: + // set it as next interrupt and return + data->interface->set_interrupt(data->queue->head->timestamp); + return; + } + } +} + +void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) { + /* disable interrupts for the duration of the function */ + __disable_irq(); + + // initialise our data + obj->timestamp = timestamp; + obj->id = id; + + /* Go through the list until we either reach the end, or find + an element this should come before (which is possibly the + head). */ + ticker_event_t *prev = NULL, *p = data->queue->head; + while (p != NULL) { + /* check if we come before p */ + if ((int)(timestamp - p->timestamp) < 0) { + break; + } + /* go to the next element */ + prev = p; + p = p->next; + } + /* if prev is NULL we're at the head */ + if (prev == NULL) { + data->queue->head = obj; + data->interface->set_interrupt(timestamp); + } else { + prev->next = obj; + } + /* if we're at the end p will be NULL, which is correct */ + obj->next = p; + + __enable_irq(); +} + +void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj) { + __disable_irq(); + + // remove this object from the list + if (data->queue->head == obj) { + // first in the list, so just drop me + data->queue->head = obj->next; + if (data->queue->head == NULL) { + data->interface->disable_interrupt(); + } else { + data->interface->set_interrupt(data->queue->head->timestamp); + } + } else { + // find the object before me, then drop me + ticker_event_t* p = data->queue->head; + while (p != NULL) { + if (p->next == obj) { + p->next = obj->next; + break; + } + p = p->next; + } + } + + __enable_irq(); +} + +timestamp_t ticker_read(const ticker_data_t *const data) +{ + return data->interface->read(); +} + +int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp) +{ + int ret = 0; + + /* if head is NULL, there are no pending events */ + __disable_irq(); + if (data->queue->head != NULL) { + *timestamp = data->queue->head->timestamp; + ret = 1; + } + __enable_irq(); + + return ret; +} diff --git a/common/us_ticker_api.c b/common/us_ticker_api.c new file mode 100644 index 0000000..0b20950 --- /dev/null +++ b/common/us_ticker_api.c @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" + +static ticker_event_queue_t events; + +static const ticker_interface_t us_interface = { + .init = us_ticker_init, + .read = us_ticker_read, + .disable_interrupt = us_ticker_disable_interrupt, + .clear_interrupt = us_ticker_clear_interrupt, + .set_interrupt = us_ticker_set_interrupt, +}; + +static const ticker_data_t us_data = { + .interface = &us_interface, + .queue = &events, +}; + +const ticker_data_t* get_us_ticker_data(void) +{ + return &us_data; +} + +void us_ticker_irq_handler(void) +{ + ticker_irq_handler(&us_data); +} diff --git a/common/wait_api.c b/common/wait_api.c new file mode 100644 index 0000000..b276614 --- /dev/null +++ b/common/wait_api.c @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "wait_api.h" +#include "us_ticker_api.h" + +void wait(float s) { + wait_us(s * 1000000.0f); +} + +void wait_ms(int ms) { + wait_us(ms * 1000); +} + +void wait_us(int us) { + uint32_t start = us_ticker_read(); + while ((us_ticker_read() - start) < (uint32_t)us); +} diff --git a/hal/analogin_api.h b/hal/analogin_api.h new file mode 100644 index 0000000..98d02c1 --- /dev/null +++ b/hal/analogin_api.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ANALOGIN_API_H +#define MBED_ANALOGIN_API_H + +#include "device.h" + +#if DEVICE_ANALOGIN + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct analogin_s analogin_t; + +void analogin_init (analogin_t *obj, PinName pin); +float analogin_read (analogin_t *obj); +uint16_t analogin_read_u16(analogin_t *obj); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/analogout_api.h b/hal/analogout_api.h new file mode 100644 index 0000000..97a2013 --- /dev/null +++ b/hal/analogout_api.h @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ANALOGOUT_API_H +#define MBED_ANALOGOUT_API_H + +#include "device.h" + +#if DEVICE_ANALOGOUT + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct dac_s dac_t; + +void analogout_init (dac_t *obj, PinName pin); +void analogout_free (dac_t *obj); +void analogout_write (dac_t *obj, float value); +void analogout_write_u16(dac_t *obj, uint16_t value); +float analogout_read (dac_t *obj); +uint16_t analogout_read_u16 (dac_t *obj); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/buffer.h b/hal/buffer.h new file mode 100644 index 0000000..2238691 --- /dev/null +++ b/hal/buffer.h @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_BUFFER_H +#define MBED_BUFFER_H + +#include + +/** Generic buffer structure + */ +typedef struct buffer_s { + void *buffer; /**< the pointer to a buffer */ + size_t length; /**< the buffer length */ + size_t pos; /**< actual buffer position */ + uint8_t width; /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */ +} buffer_t; + +#endif diff --git a/hal/can_api.h b/hal/can_api.h new file mode 100644 index 0000000..2f51cea --- /dev/null +++ b/hal/can_api.h @@ -0,0 +1,80 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CAN_API_H +#define MBED_CAN_API_H + +#include "device.h" + +#if DEVICE_CAN + +#include "PinNames.h" +#include "PeripheralNames.h" +#include "can_helper.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + IRQ_RX, + IRQ_TX, + IRQ_ERROR, + IRQ_OVERRUN, + IRQ_WAKEUP, + IRQ_PASSIVE, + IRQ_ARB, + IRQ_BUS, + IRQ_READY +} CanIrqType; + + +typedef enum { + MODE_RESET, + MODE_NORMAL, + MODE_SILENT, + MODE_TEST_LOCAL, + MODE_TEST_GLOBAL, + MODE_TEST_SILENT +} CanMode; + +typedef void (*can_irq_handler)(uint32_t id, CanIrqType type); + +typedef struct can_s can_t; + +void can_init (can_t *obj, PinName rd, PinName td); +void can_free (can_t *obj); +int can_frequency(can_t *obj, int hz); + +void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id); +void can_irq_free (can_t *obj); +void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable); + +int can_write (can_t *obj, CAN_Message, int cc); +int can_read (can_t *obj, CAN_Message *msg, int handle); +int can_mode (can_t *obj, CanMode mode); +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle); +void can_reset (can_t *obj); +unsigned char can_rderror (can_t *obj); +unsigned char can_tderror (can_t *obj); +void can_monitor (can_t *obj, int silent); + +#ifdef __cplusplus +}; +#endif + +#endif // MBED_CAN_API_H + +#endif diff --git a/hal/dma_api.h b/hal/dma_api.h new file mode 100644 index 0000000..8af5cbe --- /dev/null +++ b/hal/dma_api.h @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + * Copyright (c) 2014-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DMA_API_H +#define MBED_DMA_API_H + +#include + +#define DMA_ERROR_OUT_OF_CHANNELS (-1) + +typedef enum { + DMA_USAGE_NEVER, + DMA_USAGE_OPPORTUNISTIC, + DMA_USAGE_ALWAYS, + DMA_USAGE_TEMPORARY_ALLOCATED, + DMA_USAGE_ALLOCATED +} DMAUsage; + +#ifdef __cplusplus +extern "C" { +#endif + +void dma_init(void); + +int dma_channel_allocate(uint32_t capabilities); + +int dma_channel_free(int channelid); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/ethernet_api.h b/hal/ethernet_api.h new file mode 100644 index 0000000..4cae77e --- /dev/null +++ b/hal/ethernet_api.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ETHERNET_API_H +#define MBED_ETHERNET_API_H + +#include "device.h" + +#if DEVICE_ETHERNET + +#ifdef __cplusplus +extern "C" { +#endif + +// Connection constants + +int ethernet_init(void); +void ethernet_free(void); + +// write size bytes from data to ethernet buffer +// return num bytes written +// or -1 if size is too big +int ethernet_write(const char *data, int size); + +// send ethernet write buffer, returning the packet size sent +int ethernet_send(void); + +// recieve from ethernet buffer, returning packet size, or 0 if no packet +int ethernet_receive(void); + +// read size bytes in to data, return actual num bytes read (0..size) +// if data == NULL, throw the bytes away +int ethernet_read(char *data, int size); + +// get the ethernet address +void ethernet_address(char *mac); + +// see if the link is up +int ethernet_link(void); + +// force link settings +void ethernet_set_link(int speed, int duplex); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/hal/gpio_api.h b/hal/gpio_api.h new file mode 100644 index 0000000..872b547 --- /dev/null +++ b/hal/gpio_api.h @@ -0,0 +1,57 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_API_H +#define MBED_GPIO_API_H + +#include "device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Set the given pin as GPIO + * @param pin The pin to be set as GPIO + * @return The GPIO port mask for this pin + **/ +uint32_t gpio_set(PinName pin); + +/* Checks if gpio object is connected (pin was not initialized with NC) + * @param pin The pin to be set as GPIO + * @return 0 if port is initialized with NC + **/ +int gpio_is_connected(const gpio_t *obj); + +/* GPIO object */ +void gpio_init(gpio_t *obj, PinName pin); + +void gpio_mode (gpio_t *obj, PinMode mode); +void gpio_dir (gpio_t *obj, PinDirection direction); + +void gpio_write(gpio_t *obj, int value); +int gpio_read (gpio_t *obj); + +// the following set of functions are generic and are implemented in the common gpio.c file +void gpio_init_in(gpio_t* gpio, PinName pin); +void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode); +void gpio_init_out(gpio_t* gpio, PinName pin); +void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value); +void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/gpio_irq_api.h b/hal/gpio_irq_api.h new file mode 100644 index 0000000..76c7e92 --- /dev/null +++ b/hal/gpio_irq_api.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_IRQ_API_H +#define MBED_GPIO_IRQ_API_H + +#include "device.h" + +#if DEVICE_INTERRUPTIN + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + IRQ_NONE, + IRQ_RISE, + IRQ_FALL +} gpio_irq_event; + +typedef struct gpio_irq_s gpio_irq_t; + +typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id); +void gpio_irq_free(gpio_irq_t *obj); +void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable); +void gpio_irq_enable(gpio_irq_t *obj); +void gpio_irq_disable(gpio_irq_t *obj); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/i2c_api.h b/hal/i2c_api.h new file mode 100644 index 0000000..978f242 --- /dev/null +++ b/hal/i2c_api.h @@ -0,0 +1,223 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_I2C_API_H +#define MBED_I2C_API_H + +#include "device.h" +#include "buffer.h" + +#if DEVICE_I2C + +/** + * @defgroup I2CEvents I2C Events Macros + * + * @{ + */ +#define I2C_EVENT_ERROR (1 << 1) +#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) +#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) +#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) +#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) + +/**@}*/ + +#if DEVICE_I2C_ASYNCH +/** Asynch i2c hal structure + */ +typedef struct { + struct i2c_s i2c; /**< Target specific i2c structure */ + struct buffer_s tx_buff; /**< Tx buffer */ + struct buffer_s rx_buff; /**< Rx buffer */ +} i2c_t; + +#else +/** Non-asynch i2c hal structure + */ +typedef struct i2c_s i2c_t; + +#endif + +enum { + I2C_ERROR_NO_SLAVE = -1, + I2C_ERROR_BUS_BUSY = -2 +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup GeneralI2C I2C Configuration Functions + * @{ + */ + +/** Initialize the I2C peripheral. It sets the default parameters for I2C + * peripheral, and configure its specifieds pins. + * @param obj The i2c object + * @param sda The sda pin + * @param scl The scl pin + */ +void i2c_init(i2c_t *obj, PinName sda, PinName scl); + +/** Configure the I2C frequency. + * @param obj The i2c object + * @param hz Frequency in Hz + */ +void i2c_frequency(i2c_t *obj, int hz); + +/** Send START command. + * @param obj The i2c object + */ +int i2c_start(i2c_t *obj); + +/** Send STOP command. + * @param obj The i2c object + */ +int i2c_stop(i2c_t *obj); + +/** Blocking reading data. + * @param obj The i2c object + * @param address 7-bit address (last bit is 1) + * @param data The buffer for receiving + * @param length Number of bytes to read + * @param stop Stop to be generated after the transfer is done + * @return Number of read bytes + */ +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop); + +/** Blocking sending data. + * @param obj The i2c object + * @param address 7-bit address (last bit is 0) + * @param data The buffer for sending + * @param length Number of bytes to wrte + * @param stop Stop to be generated after the transfer is done + * @return Number of written bytes + */ +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop); + +/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop(). + * @param obj The i2c object + */ +void i2c_reset(i2c_t *obj); + +/** Read one byte. + * @param obj The i2c object + * @param last Acknoledge + * @return The read byte + */ +int i2c_byte_read(i2c_t *obj, int last); + +/** Write one byte. + * @param obj The i2c object + * @param data Byte to be written + * @return 1 if NAK was received, 0 if ACK was received, 2 for timeout. + */ +int i2c_byte_write(i2c_t *obj, int data); + +/**@}*/ + +#if DEVICE_I2CSLAVE + +/** + * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave + * @{ + */ + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @return non-zero if a value is available + */ +void i2c_slave_mode(i2c_t *obj, int enable_slave); + +/** Check to see if the I2C slave has been addressed. + * @param obj The I2C object + * @return The status - 1 - read addresses, 2 - write to all slaves, + * 3 write addressed, 0 - the slave has not been addressed + */ +int i2c_slave_receive(i2c_t *obj); + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @return non-zero if a value is available + */ +int i2c_slave_read(i2c_t *obj, char *data, int length); + +/** Configure I2C as slave or master. + * @param obj The I2C object + * @return non-zero if a value is available + */ +int i2c_slave_write(i2c_t *obj, const char *data, int length); + +/** Configure I2C address. + * @param obj The I2C object + * @param idx Currently not used + * @param address The address to be set + * @param mask Currently not used + */ +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask); + +#endif + +/**@}*/ + +#if DEVICE_I2C_ASYNCH + +/** + * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer + * @{ + */ + +/** Start i2c asynchronous transfer. + * @param obj The I2C object + * @param tx The buffer to send + * @param tx_length The number of words to transmit + * @param rx The buffer to receive + * @param rx_length The number of words to receive + * @param address The address to be set - 7bit or 9 bit + * @param stop If true, stop will be generated after the transfer is done + * @param handler The I2C IRQ handler to be set + * @param hint DMA hint usage + */ +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint); + +/** The asynchronous IRQ handler + * @param obj The I2C object which holds the transfer information + * @return event flags if a transfer termination condition was met or 0 otherwise. + */ +uint32_t i2c_irq_handler_asynch(i2c_t *obj); + +/** Attempts to determine if I2C peripheral is already in use. + * @param obj The I2C object + * @return non-zero if the I2C module is active or zero if it is not + */ +uint8_t i2c_active(i2c_t *obj); + +/** Abort ongoing asynchronous transaction. + * @param obj The I2C object + */ +void i2c_abort_asynch(i2c_t *obj); + +#endif + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/lp_ticker_api.h b/hal/lp_ticker_api.h new file mode 100644 index 0000000..7e652ea --- /dev/null +++ b/hal/lp_ticker_api.h @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_LPTICKER_API_H +#define MBED_LPTICKER_API_H + +#include "device.h" + +#if DEVICE_LOWPOWERTIMER + +#include "ticker_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup LpTicker Low Power Ticker Functions + * @{ + */ + +/** Get low power ticker's data + * + * @return The low power ticker data + */ +const ticker_data_t* get_lp_ticker_data(void); + +/** The wrapper for ticker_irq_handler, to pass lp ticker's data + * + */ +void lp_ticker_irq_handler(void); + +/* HAL lp ticker */ + +/** Initialize the low power ticker + * + */ +void lp_ticker_init(void); + +/** Read the current counter + * + * @return The current timer's counter value in microseconds + */ +uint32_t lp_ticker_read(void); + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in microseconds to be set + */ +void lp_ticker_set_interrupt(timestamp_t timestamp); + +/** Disable low power ticker interrupt + * + */ +void lp_ticker_disable_interrupt(void); + +/** Clear the low power ticker interrupt + * + */ +void lp_ticker_clear_interrupt(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/pinmap.h b/hal/pinmap.h new file mode 100644 index 0000000..a9cc921 --- /dev/null +++ b/hal/pinmap.h @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINMAP_H +#define MBED_PINMAP_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + int peripheral; + int function; +} PinMap; + +void pin_function(PinName pin, int function); +void pin_mode (PinName pin, PinMode mode); + +uint32_t pinmap_peripheral(PinName pin, const PinMap* map); +uint32_t pinmap_function(PinName pin, const PinMap* map); +uint32_t pinmap_merge (uint32_t a, uint32_t b); +void pinmap_pinout (PinName pin, const PinMap *map); +uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map); +uint32_t pinmap_find_function(PinName pin, const PinMap* map); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/port_api.h b/hal/port_api.h new file mode 100644 index 0000000..f687cfe --- /dev/null +++ b/hal/port_api.h @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTMAP_H +#define MBED_PORTMAP_H + +#include "device.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct port_s port_t; + +PinName port_pin(PortName port, int pin_n); + +void port_init (port_t *obj, PortName port, int mask, PinDirection dir); +void port_mode (port_t *obj, PinMode mode); +void port_dir (port_t *obj, PinDirection dir); +void port_write(port_t *obj, int value); +int port_read (port_t *obj); + +#ifdef __cplusplus +} +#endif +#endif + +#endif diff --git a/hal/pwmout_api.h b/hal/pwmout_api.h new file mode 100644 index 0000000..6557fcd --- /dev/null +++ b/hal/pwmout_api.h @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PWMOUT_API_H +#define MBED_PWMOUT_API_H + +#include "device.h" + +#if DEVICE_PWMOUT + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct pwmout_s pwmout_t; + +void pwmout_init (pwmout_t* obj, PinName pin); +void pwmout_free (pwmout_t* obj); + +void pwmout_write (pwmout_t* obj, float percent); +float pwmout_read (pwmout_t* obj); + +void pwmout_period (pwmout_t* obj, float seconds); +void pwmout_period_ms (pwmout_t* obj, int ms); +void pwmout_period_us (pwmout_t* obj, int us); + +void pwmout_pulsewidth (pwmout_t* obj, float seconds); +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms); +void pwmout_pulsewidth_us(pwmout_t* obj, int us); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/rtc_api.h b/hal/rtc_api.h new file mode 100644 index 0000000..663f888 --- /dev/null +++ b/hal/rtc_api.h @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_RTC_API_H +#define MBED_RTC_API_H + +#include "device.h" + +#if DEVICE_RTC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void rtc_init(void); +void rtc_free(void); +int rtc_isenabled(void); + +time_t rtc_read(void); +void rtc_write(time_t t); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/serial_api.h b/hal/serial_api.h new file mode 100644 index 0000000..6cf9a4b --- /dev/null +++ b/hal/serial_api.h @@ -0,0 +1,302 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SERIAL_API_H +#define MBED_SERIAL_API_H + +#include "device.h" +#include "buffer.h" +#include "dma_api.h" + +#if DEVICE_SERIAL + +#define SERIAL_EVENT_TX_SHIFT (2) +#define SERIAL_EVENT_RX_SHIFT (8) + +#define SERIAL_EVENT_TX_MASK (0x00FC) +#define SERIAL_EVENT_RX_MASK (0x3F00) + +#define SERIAL_EVENT_ERROR (1 << 1) + +/** + * @defgroup SerialTXEvents Serial TX Events Macros + * + * @{ + */ +#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0)) +#define SERIAL_EVENT_TX_ALL (SERIAL_EVENT_TX_COMPLETE) +/**@}*/ + +/** + * @defgroup SerialRXEvents Serial RX Events Macros + * + * @{ + */ +#define SERIAL_EVENT_RX_COMPLETE (1 << (SERIAL_EVENT_RX_SHIFT + 0)) +#define SERIAL_EVENT_RX_OVERRUN_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 1)) +#define SERIAL_EVENT_RX_FRAMING_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 2)) +#define SERIAL_EVENT_RX_PARITY_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 3)) +#define SERIAL_EVENT_RX_OVERFLOW (1 << (SERIAL_EVENT_RX_SHIFT + 4)) +#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5)) +#define SERIAL_EVENT_RX_ALL (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \ + SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \ + SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH) +/**@}*/ + +#define SERIAL_RESERVED_CHAR_MATCH (255) + +typedef enum { + ParityNone = 0, + ParityOdd = 1, + ParityEven = 2, + ParityForced1 = 3, + ParityForced0 = 4 +} SerialParity; + +typedef enum { + RxIrq, + TxIrq +} SerialIrq; + +typedef enum { + FlowControlNone, + FlowControlRTS, + FlowControlCTS, + FlowControlRTSCTS +} FlowControl; + +typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event); + +#if DEVICE_SERIAL_ASYNCH +/** Asynch serial hal structure + */ +typedef struct { + struct serial_s serial; /**< Target specific serial structure */ + struct buffer_s tx_buff; /**< Tx buffer */ + struct buffer_s rx_buff; /**< Rx buffer */ + uint8_t char_match; /**< Character to be matched */ + uint8_t char_found; /**< State of the matched character */ +} serial_t; + +#else +/** Non-asynch serial hal structure + */ +typedef struct serial_s serial_t; + +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup GeneralSerial Serial Configuration Functions + * @{ + */ + +/** Initialize the serial peripheral. It sets the default parameters for serial + * peripheral, and configure its specifieds pins. + * + * @param obj The serial object + * @param tx The TX pin + * @param rx The RX pin + */ +void serial_init(serial_t *obj, PinName tx, PinName rx); + +/** Release the serial peripheral, not currently invoked. It requires further + * resource management. + * + * @param obj The serial object + */ +void serial_free(serial_t *obj); + +/** Configure the baud rate + * + * @param obj The serial object + * @param baudrate The baud rate to be configured + */ +void serial_baud(serial_t *obj, int baudrate); + +/** Configure the format. Set the number of bits, parity and the number of stop bits + * + * @param obj The serial object + * @param data_bits The number of data bits + * @param parity The parity + * @param stop_bits The number of stop bits + */ +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits); + +/** The serial interrupt handler registration. + * + * @param obj The serial object + * @param handler The interrupt handler which will be invoked when interrupt fires. + * @param id The SerialBase object + */ +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id); + +/** Configure serial interrupt. This function is used for word-approach + * + * @param obj The serial object + * @param irq The serial IRQ type (RX or TX) + * @param enable Set to non-zero to enable events, or zero to disable them + */ +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable); + +/** Get character. This is a blocking call, waiting for a character + * + * @param obj The serial object + */ +int serial_getc(serial_t *obj); + +/** Put a character. This is a blocking call, waiting for a peripheral to be available + * for writing + * + * @param obj The serial object + * @param c The character to be sent + */ +void serial_putc(serial_t *obj, int c); + +/** Check if the serial peripheral is readable + * + * @param obj The serial object + * @return Non-zero value if a character can be read, 0 if nothing to read. + */ +int serial_readable(serial_t *obj); + +/** Check if the serial peripheral is writable + * + * @param obj The serial object + * @return Non-zero value if a character can be written, 0 otherwise. + */ +int serial_writable(serial_t *obj); + +/** Clear the serial peripheral + * + * @param obj The serial object + */ +void serial_clear(serial_t *obj); + +/** Set the break + * + * @param obj The serial object + */ +void serial_break_set(serial_t *obj); + +/** Clear the break + * + * @param obj The serial object + */ +void serial_break_clear(serial_t *obj); + +/** Configure the TX pin for UART function. + * + * @param tx The pin used for TX + */ +void serial_pinout_tx(PinName tx); + +/** Configure the serial for the flow control. It sets flow control in the hardware + * if a serial peripheral supports it, otherwise software emulation is used. + * + * @param obj The serial object + * @param type The type of the flow control. Look at the available FlowControl types. + * @param rxflow The tx pin + * @param txflow The rx pin + */ +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow); + +#if DEVICE_SERIAL_ASYNCH + +/**@}*/ + +/** + * \defgroup AsynchSerial Asynchronous Serial Hardware Abstraction Layer + * @{ + */ + +/** Begin asynchronous TX transfer. The used buffer is specified in the serial object, + * tx_buff + * + * @param obj The serial object + * @param tx The buffer for sending + * @param tx_length The number of words to transmit + * @param tx_width The bit width of buffer word + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param hint A suggestion for how to use DMA with this transfer + * @return Returns number of data transfered, or 0 otherwise + */ +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint); + +/** Begin asynchronous RX transfer (enable interrupt for data collecting) + * The used buffer is specified in the serial object - rx_buff + * + * @param obj The serial object + * @param rx The buffer for sending + * @param rx_length The number of words to transmit + * @param rx_width The bit width of buffer word + * @param handler The serial handler + * @param event The logical OR of events to be registered + * @param handler The serial handler + * @param char_match A character in range 0-254 to be matched + * @param hint A suggestion for how to use DMA with this transfer + */ +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint); + +/** Attempts to determine if the serial peripheral is already in use for TX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_tx_active(serial_t *obj); + +/** Attempts to determine if the serial peripheral is already in use for RX + * + * @param obj The serial object + * @return Non-zero if the RX transaction is ongoing, 0 otherwise + */ +uint8_t serial_rx_active(serial_t *obj); + +/** The asynchronous TX and RX handler. + * + * @param obj The serial object + * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise + */ +int serial_irq_handler_asynch(serial_t *obj); + +/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and + * flush TX hardware buffer if TX FIFO is used + * + * @param obj The serial object + */ +void serial_tx_abort_asynch(serial_t *obj); + +/** Abort the ongoing RX transaction It disables the enabled interrupt for RX and + * flush RX hardware buffer if RX FIFO is used + * + * @param obj The serial object + */ +void serial_rx_abort_asynch(serial_t *obj); + +/**@}*/ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/sleep_api.h b/hal/sleep_api.h new file mode 100644 index 0000000..c8cf3b6 --- /dev/null +++ b/hal/sleep_api.h @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SLEEP_API_H +#define MBED_SLEEP_API_H + +#include "device.h" + +#if DEVICE_SLEEP + +#ifdef __cplusplus +extern "C" { +#endif + +/** Send the microcontroller to sleep + * + * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + */ +void sleep(void); + +/** Send the microcontroller to deep sleep + * + * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode + * has the same sleep features as sleep plus it powers down peripherals and clocks. All state + * is still maintained. + * + * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + */ +void deepsleep(void); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/hal/spi_api.h b/hal/spi_api.h new file mode 100644 index 0000000..16ec74d --- /dev/null +++ b/hal/spi_api.h @@ -0,0 +1,213 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_SPI_API_H +#define MBED_SPI_API_H + +#include "device.h" +#include "dma_api.h" +#include "buffer.h" + +#if DEVICE_SPI + +#define SPI_EVENT_ERROR (1 << 1) +#define SPI_EVENT_COMPLETE (1 << 2) +#define SPI_EVENT_RX_OVERFLOW (1 << 3) +#define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW) + +#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred + +#define SPI_FILL_WORD (0xFFFF) + +#if DEVICE_SPI_ASYNCH +/** Asynch spi hal structure + */ +typedef struct { + struct spi_s spi; /**< Target specific spi structure */ + struct buffer_s tx_buff; /**< Tx buffer */ + struct buffer_s rx_buff; /**< Rx buffer */ +} spi_t; + +#else +/** Non-asynch spi hal structure + */ +typedef struct spi_s spi_t; + +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup GeneralSPI SPI Configuration Functions + * @{ + */ + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + * @param[in] mosi The pin to use for MOSI + * @param[in] miso The pin to use for MISO + * @param[in] sclk The pin to use for SCLK + * @param[in] ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel); + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * @param[in] obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj); + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode + * @param[in,out] obj The SPI object to configure + * @param[in] bits The number of bits per frame + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] slave Zero for master mode or non-zero for slave mode + */ +void spi_format(spi_t *obj, int bits, int mode, int slave); + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz); + +/**@}*/ +/** + * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer + * @{ + */ + +/** Write a byte out in master mode and receive a value + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value); + +/** Check if a value is available to read + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if a value is available + */ +int spi_slave_receive(spi_t *obj); + +/** Get a received value out of the SPI receive buffer in slave mode + * + * Blocks until a value is available + * @param[in] obj The SPI peripheral to read + * @return The value received + */ +int spi_slave_read(spi_t *obj); + +/** Write a value to the SPI peripheral in slave mode + * + * Blocks until the SPI peripheral can be written to + * @param[in] obj The SPI peripheral to write + * @param[in] value The value to write + */ +void spi_slave_write(spi_t *obj, int value); + +/** Checks if the specified SPI peripheral is in use + * + * @param[in] obj The SPI peripheral to check + * @return non-zero if the peripheral is currently transmitting + */ +int spi_busy(spi_t *obj); + +/** Get the module number + * + * @param[in] obj The SPI peripheral to check + * @return The module number + */ +uint8_t spi_get_module(spi_t *obj); + +/**@}*/ + +#if DEVICE_SPI_ASYNCH +/** + * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer + * @{ + */ + +/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff + * + * @param[in] obj The SPI object which holds the transfer information + * @param[in] tx The buffer to send + * @param[in] tx_length The number of words to transmit + * @param[in] rx The buffer to receive + * @param[in] rx_length The number of words to receive + * @param[in] bit_width The bit width of buffer words + * @param[in] event The logical OR of events to be registered + * @param[in] handler SPI interrupt handler + * @param[in] hint A suggestion for how to use DMA with this transfer + */ +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint); + +/** The asynchronous IRQ handler + * + * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination + * conditions, such as buffer overflows or transfer complete. + * @param[in] obj The SPI object which holds the transfer information + * @return event flags if a transfer termination condition was met or 0 otherwise. + */ +uint32_t spi_irq_handler_asynch(spi_t *obj); + +/** Attempts to determine if the SPI peripheral is already in use. + * + * If a temporary DMA channel has been allocated, peripheral is in use. + * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA + * channel were allocated. + * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check + * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if + * there are any bytes in the FIFOs. + * @param[in] obj The SPI object to check for activity + * @return non-zero if the SPI port is active or zero if it is not. + */ +uint8_t spi_active(spi_t *obj); + +/** Abort an SPI transfer + * + * @param obj The SPI peripheral to stop + */ +void spi_abort_asynch(spi_t *obj); + + +#endif + +/**@}*/ + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // SPI_DEVICE + +#endif // MBED_SPI_API_H diff --git a/hal/ticker_api.h b/hal/ticker_api.h new file mode 100644 index 0000000..5f24d27 --- /dev/null +++ b/hal/ticker_api.h @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TICKER_API_H +#define MBED_TICKER_API_H + +#include "device.h" + +typedef uint32_t timestamp_t; + +/** Ticker's event structure + */ +typedef struct ticker_event_s { + timestamp_t timestamp; /**< Event's timestamp */ + uint32_t id; /**< TimerEvent object */ + struct ticker_event_s *next; /**< Next event in the queue */ +} ticker_event_t; + +typedef void (*ticker_event_handler)(uint32_t id); + +/** Ticker's interface structure - required API for a ticker + */ +typedef struct { + void (*init)(void); /**< Init function */ + uint32_t (*read)(void); /**< Read function */ + void (*disable_interrupt)(void); /**< Disable interrupt function */ + void (*clear_interrupt)(void); /**< Clear interrupt function */ + void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */ +} ticker_interface_t; + +/** Tickers events queue structure + */ +typedef struct { + ticker_event_handler event_handler; /**< Event handler */ + ticker_event_t *head; /**< A pointer to head */ +} ticker_event_queue_t; + +/** Tickers data structure + */ +typedef struct { + const ticker_interface_t *interface; /**< Ticker's interface */ + ticker_event_queue_t *queue; /**< Ticker's events queue */ +} ticker_data_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** Initialize a ticker and sets the event handler + * + * @param data The ticker's data + * @param handler A handler to be set + */ +void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler); + +/** Irq handler which goes through the events to trigger events in the past. + * + * @param data The ticker's data + */ +void ticker_irq_handler(const ticker_data_t *const data); + +/** Remove an event from the queue + * + * @param data The ticker's data + * @param obj The event's queue to be removed + */ +void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj); + +/** Insert an event from the queue + * + * @param data The ticker's data + * @param obj The event's queue to be removed + * @param timestamp The event's timestamp + * @param id The event object + */ +void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id); + +/** Read the current ticker's timestamp + * + * @param data The ticker's data + * @return The current timestamp + */ +timestamp_t ticker_read(const ticker_data_t *const data); + +/** Read the next event's timestamp + * + * @param data The ticker's data + * @return 1 if timestamp is pending event, 0 if there's no event pending + */ +int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hal/us_ticker_api.h b/hal/us_ticker_api.h new file mode 100644 index 0000000..b5c78de --- /dev/null +++ b/hal/us_ticker_api.h @@ -0,0 +1,78 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_US_TICKER_API_H +#define MBED_US_TICKER_API_H + +#include +#include "ticker_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \defgroup UsTicker Microseconds Ticker Functions + * @{ + */ + +/** Get ticker's data + * + * @return The low power ticker data + */ +const ticker_data_t* get_us_ticker_data(void); + + +/** The wrapper for ticker_irq_handler, to pass us ticker's data + * + */ +void us_ticker_irq_handler(void); + +/* HAL us ticker */ + +/** Initialize the ticker + * + */ +void us_ticker_init(void); + +/** Read the current counter + * + * @return The current timer's counter value in microseconds + */ +uint32_t us_ticker_read(void); + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in microseconds to be set + */ +void us_ticker_set_interrupt(timestamp_t timestamp); + +/** Disable us ticker interrupt + * + */ +void us_ticker_disable_interrupt(void); + +/** Clear us ticker interrupt + * + */ +void us_ticker_clear_interrupt(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/module.json b/module.json new file mode 100644 index 0000000..6f7066a --- /dev/null +++ b/module.json @@ -0,0 +1,28 @@ +{ + "name": "mbed-classic", + "version": "0.0.4", + "description": "mbed core SDK (for mbed 2.0, *not* mbedOS)", + "keywords": [ + "mbed" + ], + "author": "Bogdan Marinescu ", + "repository": { + "url": "git@github.com:mbedmicro/mbed.git", + "type": "git" + }, + "homepage": "https://github.com/mbedmicro/mbed", + "licenses": [ + { + "url": "https://spdx.org/licenses/Apache-2.0", + "type": "Apache-2.0" + } + ], + "extraIncludes": [ + "api", + "hal", + "targets/hal", + "targets/cmsis" + ], + "dependencies": {}, + "targetDependencies": {} +} \ No newline at end of file diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h new file mode 100644 index 0000000..b07dfc6 --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/CMSDK_CM0.h @@ -0,0 +1,725 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM0.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_CM0 Device +* @version V3.02 +* @date 15. November 2013 +* +* @note configured for CM7 without FPU +* +*******************************************************************************/ + + +#ifndef CMSDK_CM0_H +#define CMSDK_CM0_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM0 Specific Interrupt Numbers ------------------ */ + UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ + PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI_IRQn = 11, /* SPI Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /* Ethernet Interrupt */ + I2S_IRQn = 14, /* I2S Interrupt */ + TSC_IRQn = 15, /* Touch Screen Interrupt */ +// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ + PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ + PORT0_1_IRQn = 17, /* There are 16 pins in total */ + PORT0_2_IRQn = 18, + PORT0_3_IRQn = 19, + PORT0_4_IRQn = 20, + PORT0_5_IRQn = 21, + PORT0_6_IRQn = 22, + PORT0_7_IRQn = 23, + PORT0_8_IRQn = 24, + PORT0_9_IRQn = 25, + PORT0_10_IRQn = 26, + PORT0_11_IRQn = 27, + PORT0_12_IRQn = 28, + PORT0_13_IRQn = 29, + PORT0_14_IRQn = 30, + PORT0_15_IRQn = 31, +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */ +#define __CM0_REV 0x0000 /* Core revision r0p0 */ +#define __MPU_PRESENT 0 /* MPU present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_CM0.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */ + __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */ + __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */ + __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */ + __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */ + __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */ + __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */ + __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */ + __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */ + uint32_t RESERVED0[3]; + __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */ + +} CMSDK_PL230_TypeDef; + +#define PL230_DMA_CHNL_BITS 0 + +#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */ +#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */ +#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */ + +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */ +#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */ + +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */ +#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */ + +#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */ +#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */ +#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */ +#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */ + +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */ +#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */ + +#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */ +#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */ + +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */ +#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */ + +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */ +#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */ + +#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */ +#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */ +#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */ + +#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */ +#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */ + +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */ +#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */ +#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */ + +#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */ +#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */ + +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */ +#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */ +#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */ + +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */ +#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */ + +#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */ +#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined ( __CC_ARM ) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE ) +#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_M0_H */ diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h new file mode 100644 index 0000000..910d5ab --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/SMM_MPS2.h @@ -0,0 +1,595 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* File: smm_mps2.h +* Release: Version 1.0 +*******************************************************************************/ + +#ifndef __SMM_MPS2_H +#define __SMM_MPS2_H + +#include "peripherallink.h" /* device specific header file */ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections + // [31:2] : Reserved + // [1:0] : LEDs + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons + // [31:2] : Reserved + // [1:0] : Buttons + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter + __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter + __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter + // Increments when 32-bit prescale counter reach zero + uint32_t RESERVED3[1]; + __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler + // Bit[31:0] : reload value for prescale counter + __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter + // current value of the pre-scaler counter + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + uint32_t RESERVED4[9]; + __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ + // [31:7] : Reserved + // [6] : CLCD_BL_CTRL + // [5] : CLCD_RD + // [4] : CLCD_RS + // [3] : CLCD_RESET + // [2] : RESERVED + // [1] : SPI_nSS + // [0] : CLCD_CS +} MPS2_FPGAIO_TypeDef; + +// MISC register bit definitions + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + // TX Enable + // <0=> TX disabled + // <1=> TX enabled + // TX IRQ Enable + // <0=> TX IRQ disabled + // <1=> TX IRQ enabled + // RX Enable + // <0=> RX disabled + // <1=> RX enabled + // RX IRQ Enable + // <0=> RX IRQ disabled + // <1=> RX IRQ enabled + // TX Buffer Water Level + // <0=> / IRQ triggers when any space available + // <1=> / IRQ triggers when more than 1 space available + // <2=> / IRQ triggers when more than 2 space available + // <3=> / IRQ triggers when more than 3 space available + // <4=> Undefined! + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // RX Buffer Water Level + // <0=> Undefined! + // <1=> / IRQ triggers when less than 1 space available + // <2=> / IRQ triggers when less than 2 space available + // <3=> / IRQ triggers when less than 3 space available + // <4=> / IRQ triggers when less than 4 space available + // <5=> Undefined! + // <6=> Undefined! + // <7=> Undefined! + // FIFO reset + // <0=> Normal operation + // <1=> FIFO reset + // Audio Codec reset + // <0=> Normal operation + // <1=> Assert audio Codec reset + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; // STATUS + // TX Buffer alert + // <0=> TX buffer don't need service yet + // <1=> TX buffer need service + // RX Buffer alert + // <0=> RX buffer don't need service yet + // <1=> RX buffer need service + // TX Buffer Empty + // <0=> TX buffer have data + // <1=> TX buffer empty + // TX Buffer Full + // <0=> TX buffer not full + // <1=> TX buffer full + // RX Buffer Empty + // <0=> RX buffer have data + // <1=> RX buffer empty + // RX Buffer Full + // <0=> RX buffer not full + // <1=> RX buffer full + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // ERROR + // TX error + // <0=> Okay + // <1=> TX overrun/underrun + // RX error + // <0=> Okay + // <1=> RX overrun/underrun + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // ERRORCLR + // TX error + // <0=> Okay + // <1=> Clear TX error + // RX error + // <0=> Okay + // <1=> Clear RX error + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock + // TX error (default 0x80) + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; // Transmit buffer + // Right channel + // Left channel + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; // Receive buffer + // Right channel + // Left channel + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; // Integration Test Control Register + // ITEN + // <0=> Normal operation + // <1=> Integration Test mode enable + __O uint32_t ITIP1; // Integration Test Input Register 1 + // SDIN + __O uint32_t ITOP1; // Integration Test Output Register 1 + // SDOUT + // SCLK + // LRCK + // IRQOUT +} MPS2_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL<>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h new file mode 100644 index 0000000..14cc79d --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis.h @@ -0,0 +1,42 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* A generic CMSIS include header, pulling in MPS2 specifics +*******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "CMSDK_CM0.h" +#include "SMM_MPS2.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c new file mode 100644 index 0000000..837273b --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.c @@ -0,0 +1,54 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* CMSIS-style functionality to support dynamic vectors +*******************************************************************************/ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + // int i; + // Space for dynamic vectors, initialised to allocate in R/W + static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + + // Set the vector + vectors[IRQn + 16] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + // We can always read vectors at 0x0, as the addresses are remapped + uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS; + + // Return the vector + return vectors[IRQn + 16]; +} diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h new file mode 100644 index 0000000..3d3a3e2 --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* CMSIS-style functionality to support dynamic vectors +*******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_NUM_VECTORS (16 + 32) +#define NVIC_USER_IRQ_OFFSET 16 + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h new file mode 100644 index 0000000..94c315a --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/peripherallink.h @@ -0,0 +1,53 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* Name: Device.h +* Purpose: Include the correct device header file +*******************************************************************************/ + +#ifndef __DEVICE_H +#define __DEVICE_H + +#if defined CMSDK_CM0 + #include "CMSDK_CM0.h" /* device specific header file */ +#elif defined CMSDK_CM0plus + #include "CMSDK_CM0plus.h" /* device specific header file */ +#elif defined CMSDK_CM3 + #include "CMSDK_CM3.h" /* device specific header file */ +#elif defined CMSDK_CM4 + #include "CMSDK_CM4.h" /* device specific header file */ +#elif defined CMSDK_CM7 + #include "CMSDK_CM7.h" /* device specific header file */ +#else + #warning "no appropriate header file found!" +#endif + +#endif /* __DEVICE_H */ diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c new file mode 100644 index 0000000..f1c17e2 --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.c @@ -0,0 +1,92 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file system_CMSDK_CM0.c +* @brief CMSIS Device System Source File for +* CMSDK_M0 Device +* @version V3.02 +* @date 15. November 2013 +* +* @note +* +*******************************************************************************/ + + +#include "CMSDK_CM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (50000000UL) /* Oscillator frequency */ + +#define __SYSTEM_CLOCK (__XTAL / 2) + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + + SystemCoreClock = __SYSTEM_CLOCK; + +} diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h new file mode 100644 index 0000000..e6bd21b --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0/system_CMSDK_CM0.h @@ -0,0 +1,80 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************* +* @file system_CMSDK_CM0.h +* @brief CMSIS Device Peripheral Access Layer Header File for +* CMSDK_CM0 Device +* @version V3.02 +* @date 15. March 2013 +* +* @note +* +******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM0_H +#define SYSTEM_CMSDK_CM0_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM0_H */ diff --git a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h new file mode 100644 index 0000000..4689f19 --- /dev/null +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h @@ -0,0 +1,726 @@ +/* MPS2 CMSIS Library +* +* Copyright (c) 2006-2015 ARM Limited +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +* @file CMSDK_CM0plus.h +* @brief CMSIS Core Peripheral Access Layer Header File for +* CMSDK_CM0plus Device +* @version V3.02 +* @date 15. November 2013 +* +* @note configured for CM7 without FPU +* +*******************************************************************************/ + + +#ifndef CMSDK_CM0plus_H +#define CMSDK_CM0plus_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers -------------- */ + UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */ + UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */ + UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */ + UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */ + UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */ + UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */ + PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */ + PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */ + TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ + TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ + SPI_IRQn = 11, /* SPI Interrupt */ + UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ + ETHERNET_IRQn = 13, /* Ethernet Interrupt */ + I2S_IRQn = 14, /* I2S Interrupt */ + TSC_IRQn = 15, /* Touch Screen Interrupt */ +// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */ + PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ + PORT0_1_IRQn = 17, /* There are 16 pins in total */ + PORT0_2_IRQn = 18, + PORT0_3_IRQn = 19, + PORT0_4_IRQn = 20, + PORT0_5_IRQn = 21, + PORT0_6_IRQn = 22, + PORT0_7_IRQn = 23, + PORT0_8_IRQn = 24, + PORT0_9_IRQn = 25, + PORT0_10_IRQn = 26, + PORT0_11_IRQn = 27, + PORT0_12_IRQn = 28, + PORT0_13_IRQn = 29, + PORT0_14_IRQn = 30, + PORT0_15_IRQn = 31, +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */ +#define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */ +#define __MPU_PRESENT 1 /* MPU present or not */ +#define __VTOR_PRESENT 1 /* VTOR present or not */ +#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#include /* Processor and core peripherals */ +#include "system_CMSDK_CM0plus.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined ( __CC_ARM ) + #pragma push +#pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ + +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */ + +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */ + +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */ + +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ + __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ + __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ + __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ + __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + +#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */ + +#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */ +#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */ +#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */ + + +typedef struct +{ + __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */ + __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */ + __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */ + +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + + +/*------------- PL230 uDMA (PL230) --------------------------------------*/ +typedef struct +{ + __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */ + __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */ + __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */ + __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */ + __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */ + __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */ + __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */ + __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear R